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GET /api/patches/2216091/?format=api
{ "id": 2216091, "url": "http://patchwork.ozlabs.org/api/patches/2216091/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325192601.239554-6-jonathanh@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325192601.239554-6-jonathanh@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T19:25:55", "name": "[05/10] soc/tegra: pmc: Add support for SoC specific AOWAKE offsets", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f7c4067b2a4c5d4889f73a774d2cdc1f3a3f001f", "submitter": { "id": 66273, "url": "http://patchwork.ozlabs.org/api/people/66273/?format=api", "name": "Jon Hunter", "email": "jonathanh@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325192601.239554-6-jonathanh@nvidia.com/mbox/", "series": [ { "id": 497504, "url": "http://patchwork.ozlabs.org/api/series/497504/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497504", "date": "2026-03-25T19:25:50", "name": "soc/tegra: pmc: Fixes and updates for Tegra264", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497504/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216091/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216091/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13247-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=PZIz7pVG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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pr=C", "From": "Jon Hunter <jonathanh@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>", "CC": "<linux-tegra@vger.kernel.org>, Jon Hunter <jonathanh@nvidia.com>", "Subject": "[PATCH 05/10] soc/tegra: pmc: Add support for SoC specific AOWAKE\n offsets", "Date": "Wed, 25 Mar 2026 19:25:55 +0000", "Message-ID": "<20260325192601.239554-6-jonathanh@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260325192601.239554-1-jonathanh@nvidia.com>", "References": "<20260325192601.239554-1-jonathanh@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF0001AB4D:EE_|LV8PR12MB9082:EE_", "X-MS-Office365-Filtering-Correlation-Id": "113ecf96-3e98-4203-e0f3-08de8aa4741a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|376014|82310400026|36860700016|1800799024|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\tuqqFGS98RDWkrNaWQbVesS+xZiT6oeHZbFLva4flCHIeR4XObHs8JR3aL+uLa78VqcQe1gzSQSL37Af2/659akre4LlQwb/qsZSAhVmy4QPk0LVLe2zcYbt8pPMI+nFFoI0DiWLCfq9Z2XRb9yhxNoJvT4oxDhj/V+AxlkgqY2qYiVDlmFl+NaVZT9gOxxXm7OmcfaFc5MCVxp1pImUO1/CRFR7HSRXKsRb8vODF8tdhHn6LUYP5eeM+aqHQResSu3izyTnSioIta6+uwVjhejkPr1EfBP+Em6AoYY62DLVLnYsmjRg5D5HK/jkkP0GAk1G5Z0LFw/6YFCx4+njDJElSwJxlQ7RpC4NvodkEnPikYfxUX6pFZmXHlX0L6MTMWf77zddST16jKK1bvQA3xXaF6UZa2jnXpuwrkeiTBD1fW7bvZp2b4TbvIuUsaqVsycAgP+3VIJLz11U+iQLQFHoGvOMJ5mNANaTM3qhaMHH5wNaxlhh4bOA1LBoGio+IEOoQFoMeq8KwbZ7qIFyWUpvKypUoPDIw8YTnXuGm/qF6TCamJcY41OA3feGlQ5nsPOp1mkHmT/moShunx6K4UIEKFSZKLwcAgT6J4Q/OCE5rj8Y3a4UeEWgNleq7sQ05x1j8nzkFcFz4Nc1ReJXvQQ0QizVGDbA2Kh0nRsQAnki/5RiSOZbeLgH4Rw/eIjHmi/Aw1rOYIMjDXRljQWqeZ4Yak1II0SIoJJNr/VN9/E3kuaPp5/QYfZoWPHaADcBXTwSEV/a+4jQqLgPwrT0QXA==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700016)(1800799024)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tkk6Oa43d/oM+mPRrfYEshjYy8UcbiBNTetp/Rd+0Is+Rm0cwHfGZ95SDsKY6eNs3/Ck4Ow/coCbnml3NesswN6gPzrArGBboYwPqfVhLd8ppH8Ll9yHuM5JxNAH3Pfu/9VhCFEArUmq6w1xNivc+LJwNXxmcmLY89H6Zs5iqF1w841ltGzOlMPPK8A4TjeROliw7CQT6zI3nMGr5UjKBVotm1K3yBjLs9jwj0LriBvR+fS/AqyhSJJkaEwmjjjewsXrbxhed0vx+m5fmDmt9ZwkgK1DLQZDqWAWB1TjNhF15rc+McOXg38PTjdKbEt4KhjSCXMDxpKG1m6YxuQUbDRDCl2STUdCZlqZBpZ+Tqo5AQ80AuBeyI2TYm8pqObchNr5JJT5c9Ty3A5UQx1OIs2iw1eZ8SkTUR3ytH0qhJ+MuFK11hnaNvS5iRK3L9BO7", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 19:26:45.8454\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 113ecf96-3e98-4203-e0f3-08de8aa4741a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL6PEPF0001AB4D.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV8PR12MB9082" }, "content": "For Tegra264, some of the AOWAKE registers have different register\noffsets. Prepare for adding the Tegra264 AOWAKE register by moving the\noffsets for the AOWAKE registers that are different for Tegra264 into\nthe 'tegra_pmc_regs' structure and populate these offsets for the SoCs\nthat support these registers.\n\nSigned-off-by: Jon Hunter <jonathanh@nvidia.com>\n---\n drivers/soc/tegra/pmc.c | 86 +++++++++++++++++++++++++++++------------\n 1 file changed, 61 insertions(+), 25 deletions(-)", "diff": "diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex 55c1117b1741..42176abb96ea 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -180,16 +180,18 @@\n #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))\n #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)\n #define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN (1 << 1)\n-#define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))\n-#define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))\n-#define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))\n-#define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))\n-#define WAKE_AOWAKE_SW_STATUS_W_0\t0x49c\n-#define WAKE_AOWAKE_SW_STATUS(x)\t(0x4a0 + ((x) << 2))\n-#define WAKE_LATCH_SW\t\t\t0x498\n-\n-#define WAKE_AOWAKE_CTRL 0x4f4\n-#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)\n+#define WAKE_AOWAKE_MASK_W(_pmc, x) \\\n+\t((_pmc)->soc->regs->aowake_mask_w + ((x) << 2))\n+#define WAKE_AOWAKE_STATUS_W(_pmc, x) \\\n+\t((_pmc)->soc->regs->aowake_status_w + ((x) << 2))\n+#define WAKE_AOWAKE_STATUS_R(_pmc, x) \\\n+\t((_pmc)->soc->regs->aowake_status_r + ((x) << 2))\n+#define WAKE_AOWAKE_TIER2_ROUTING(_pmc, x) \\\n+\t((_pmc)->soc->regs->aowake_tier2_routing + ((x) << 2))\n+#define WAKE_AOWAKE_SW_STATUS(_pmc, x) \\\n+\t((_pmc)->soc->regs->aowake_sw_status + ((x) << 2))\n+\n+#define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)\n \n #define SW_WAKE_ID\t\t83 /* wake83 */\n \n@@ -302,6 +304,14 @@ struct tegra_pmc_regs {\n \tunsigned int rst_source_mask;\n \tunsigned int rst_level_shift;\n \tunsigned int rst_level_mask;\n+\tunsigned int aowake_mask_w;\n+\tunsigned int aowake_status_w;\n+\tunsigned int aowake_status_r;\n+\tunsigned int aowake_tier2_routing;\n+\tunsigned int aowake_sw_status_w;\n+\tunsigned int aowake_sw_status;\n+\tunsigned int aowake_latch_sw;\n+\tunsigned int aowake_ctrl;\n };\n \n struct tegra_wake_event {\n@@ -2629,20 +2639,20 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)\n \tbit = data->hwirq % 32;\n \n \t/* clear wake status */\n-\twritel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));\n+\twritel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(pmc, data->hwirq));\n \n \t/* route wake to tier 2 */\n-\tvalue = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));\n+\tvalue = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, offset));\n \n \tif (!on)\n \t\tvalue &= ~(1 << bit);\n \telse\n \t\tvalue |= 1 << bit;\n \n-\twritel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));\n+\twritel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, offset));\n \n \t/* enable wakeup event */\n-\twritel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));\n+\twritel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(pmc, data->hwirq));\n \n \treturn 0;\n }\n@@ -3309,7 +3319,7 @@ static void wke_write_wake_levels(struct tegra_pmc *pmc)\n \n static void wke_clear_sw_wake_status(struct tegra_pmc *pmc)\n {\n-\twke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0);\n+\twke_32kwritel(pmc, 1, pmc->soc->regs->aowake_sw_status_w);\n }\n \n static void wke_read_sw_wake_status(struct tegra_pmc *pmc)\n@@ -3322,7 +3332,7 @@ static void wke_read_sw_wake_status(struct tegra_pmc *pmc)\n \n \twke_clear_sw_wake_status(pmc);\n \n-\twke_32kwritel(pmc, 1, WAKE_LATCH_SW);\n+\twke_32kwritel(pmc, 1, pmc->soc->regs->aowake_latch_sw);\n \n \t/*\n \t * WAKE_AOWAKE_SW_STATUS is edge triggered, so in order to\n@@ -3340,12 +3350,12 @@ static void wke_read_sw_wake_status(struct tegra_pmc *pmc)\n \t */\n \tudelay(300);\n \n-\twke_32kwritel(pmc, 0, WAKE_LATCH_SW);\n+\twke_32kwritel(pmc, 0, pmc->soc->regs->aowake_latch_sw);\n \n \tbitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events);\n \n \tfor (i = 0; i < pmc->soc->max_wake_vectors; i++) {\n-\t\tstatus = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i));\n+\t\tstatus = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(pmc, i));\n \n \t\tfor_each_set_bit(wake, &status, 32)\n \t\t\tset_bit(wake + (i * 32), pmc->wake_sw_status_map);\n@@ -3359,11 +3369,12 @@ static void wke_clear_wake_status(struct tegra_pmc *pmc)\n \tu32 mask;\n \n \tfor (i = 0; i < pmc->soc->max_wake_vectors; i++) {\n-\t\tmask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));\n-\t\tstatus = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;\n+\t\tmask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, i));\n+\t\tstatus = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(pmc, i)) & mask;\n \n \t\tfor_each_set_bit(wake, &status, 32)\n-\t\t\twke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake));\n+\t\t\twke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W(pmc,\n+\t\t\t\t\t\t\t(i * 32) + wake));\n \t}\n }\n \n@@ -3374,8 +3385,9 @@ static void tegra186_pmc_wake_syscore_resume(void *data)\n \tu32 mask;\n \n \tfor (i = 0; i < pmc->soc->max_wake_vectors; i++) {\n-\t\tmask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));\n-\t\tpmc->wake_status[i] = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;\n+\t\tmask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(pmc, i));\n+\t\tpmc->wake_status[i] = readl(pmc->wake +\n+\t\t\t\t\t WAKE_AOWAKE_STATUS_R(pmc, i)) & mask;\n \t}\n \n \t/* Schedule IRQ work to process wake IRQs (if any) */\n@@ -4062,6 +4074,14 @@ static const struct tegra_pmc_regs tegra186_pmc_regs = {\n \t.rst_source_mask = 0x3c,\n \t.rst_level_shift = 0x0,\n \t.rst_level_mask = 0x3,\n+\t.aowake_mask_w = 0x180,\n+\t.aowake_status_w = 0x30c,\n+\t.aowake_status_r = 0x48c,\n+\t.aowake_tier2_routing = 0x4cc,\n+\t.aowake_sw_status_w = 0x49c,\n+\t.aowake_sw_status = 0x4a0,\n+\t.aowake_latch_sw = 0x498,\n+\t.aowake_ctrl = 0x4f4,\n };\n \n static void tegra186_pmc_init(struct tegra_pmc *pmc)\n@@ -4094,14 +4114,14 @@ static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,\n \t\treturn;\n \t}\n \n-\tvalue = readl(wake + WAKE_AOWAKE_CTRL);\n+\tvalue = readl(wake + pmc->soc->regs->aowake_ctrl);\n \n \tif (invert)\n \t\tvalue |= WAKE_AOWAKE_CTRL_INTR_POLARITY;\n \telse\n \t\tvalue &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;\n \n-\twritel(value, wake + WAKE_AOWAKE_CTRL);\n+\twritel(value, wake + pmc->soc->regs->aowake_ctrl);\n \n \tiounmap(wake);\n }\n@@ -4281,6 +4301,14 @@ static const struct tegra_pmc_regs tegra194_pmc_regs = {\n \t.rst_source_mask = 0x7c,\n \t.rst_level_shift = 0x0,\n \t.rst_level_mask = 0x3,\n+\t.aowake_mask_w = 0x180,\n+\t.aowake_status_w = 0x30c,\n+\t.aowake_status_r = 0x48c,\n+\t.aowake_tier2_routing = 0x4cc,\n+\t.aowake_sw_status_w = 0x49c,\n+\t.aowake_sw_status = 0x4a0,\n+\t.aowake_latch_sw = 0x498,\n+\t.aowake_ctrl = 0x4f4,\n };\n \n static const char * const tegra194_reset_sources[] = {\n@@ -4400,6 +4428,14 @@ static const struct tegra_pmc_regs tegra234_pmc_regs = {\n \t.rst_source_mask = 0xfc,\n \t.rst_level_shift = 0x0,\n \t.rst_level_mask = 0x3,\n+\t.aowake_mask_w = 0x180,\n+\t.aowake_status_w = 0x30c,\n+\t.aowake_status_r = 0x48c,\n+\t.aowake_tier2_routing = 0x4cc,\n+\t.aowake_sw_status_w = 0x49c,\n+\t.aowake_sw_status = 0x4a0,\n+\t.aowake_latch_sw = 0x498,\n+\t.aowake_ctrl = 0x4f4,\n };\n \n static const char * const tegra234_reset_sources[] = {\n", "prefixes": [ "05/10" ] }