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GET /api/patches/2216085/?format=api
{ "id": 2216085, "url": "http://patchwork.ozlabs.org/api/patches/2216085/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325192601.239554-9-jonathanh@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325192601.239554-9-jonathanh@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T19:25:58", "name": "[08/10] soc/tegra: pmc: Refactor IO pad voltage control", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "902726bc2453bb521506f0dff793b1fa44190046", "submitter": { "id": 66273, "url": "http://patchwork.ozlabs.org/api/people/66273/?format=api", "name": "Jon Hunter", "email": "jonathanh@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325192601.239554-9-jonathanh@nvidia.com/mbox/", "series": [ { "id": 497504, "url": "http://patchwork.ozlabs.org/api/series/497504/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497504", "date": "2026-03-25T19:25:50", "name": "soc/tegra: pmc: Fixes and updates for Tegra264", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497504/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216085/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216085/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13253-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=AusamGwR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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pr=C", "From": "Jon Hunter <jonathanh@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>", "CC": "<linux-tegra@vger.kernel.org>, Jon Hunter <jonathanh@nvidia.com>", "Subject": "[PATCH 08/10] soc/tegra: pmc: Refactor IO pad voltage control", "Date": "Wed, 25 Mar 2026 19:25:58 +0000", "Message-ID": "<20260325192601.239554-9-jonathanh@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260325192601.239554-1-jonathanh@nvidia.com>", "References": "<20260325192601.239554-1-jonathanh@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF0001AB50:EE_|DM4PR12MB5937:EE_", "X-MS-Office365-Filtering-Correlation-Id": "219e6112-e8e4-47f4-b4a5-08de8aa476ef", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tvVhhVvMxYD1FqUirw9WszJcfhueT/LAqdoGQFLrqq/xhz5qEqYPANNHEUbtToqAKI8iu32igk5JJWgnWuijI/gU/N4+dZkZ3ueCbvCS255CGQRqCUzSs65k0Rxl7Tdf7vacZnbSmiy2l1lilK7Irl+lG95qivyAmYu5P+fjSXv6srNrP0FwekvGz6yH7+mH4/LUzaFnVXWtBAdTX2hgLKUYJRYhu86cL6rGkJ/cNZbo7KvEwojO1AS8Hq/5+ddh59/T+ZYLpEKFVVZ+Dw0CJc/e78rUxjkuufCMBttWv8W6dNIFMWwG1WbPZc+X9RrP7RHJ7JuvepXjdymR+Y4vjGt0CgDeYVzCOhDaPEBfF8CsGe/UMSRoKNFgIh6/JiotaXhigOF8nZsGENhzmBgC4+aR3UnUbqyBGp3U8PRtlsapXQ4C6/0J3CwtbMtdYiJekrbgCOTGpZnJjhJ4HraOYY68vszjpAifNGE+sk7NXsu2aU26eq4ks5+OyDOczn1r96d2ilpZIi1q7OmO+Wk22+za74eBu/BAGbGTlnP27Mgrz/jWyXNnLBoekMw46PLfMp1e/ZDWXW4B11Ek6Xm/qDoUibOq/9zk6qGCngMbeapS8Ydd2y0Lta6Aq7H5cl4d2W383TOv0pArZVyUPFnaXmT8SVR3zD7gMCQuM3PWT9F3xXZq3ONITDabyZJ8mXikh1lV/S24nWghSgnfa3fEPkwiT9z9NLYwYI6Uk/06jsvX0zX/dw0nAQMLR3ELMayVPbXzbn64GEhvWIzBWGXbZtg==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t5QRLekgP5dT2hjkVkoCa+gtmtvSRcTM0NPdkm4Pv2Af6V1VltmhKir2shw6pWN/yt0uqNZeX1DyibGv07Mpj7J1kwIgQPINnUTjTXDR6HvgtAkwHK51+tfZYwBSQJO1zWMgcmjb30phsdvGafIvCI/sNSTfgzmTkGDCoEzfmTFQighjhvsLTU+QO/X0hYuZ9eKctdMS7xXCkO0SfOBCmmNlAA7i+H1/jckpdCQhhIyo00+ryjILUEuvP6QhIo5ay3FKcY9MgJsVMpHNxTJrWRBbM2bKeIeqWZWDBIJGQaIe2VKY/cj1S0Aat1K4lMQ6vSRylrlmtmoycNrfkxJOo+EhyPN4Ixwd+y+P+wZI3ckQd1Kg5IGH5z+b9xIuuMnHKR+O1nQAq9LlsEurlOtxC2xV75n/Bt+YaVR4kLX+UmkkjfliiGPATvc4DLqVMV7U7", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 19:26:50.5922\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 219e6112-e8e4-47f4-b4a5-08de8aa476ef", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL6PEPF0001AB50.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5937" }, "content": "For Tegra devices, only a subset of IO pads can be configured for 1.8V\nor 3.3V. Therefore, in the 'tegra_io_pad_soc' structure for Tegra SoCs\neither all or most of the 'voltage' entries are set to UINT_MAX to\nindicate the IO pad voltage cannot be configured. So for the majority of\nIO pads this configuration is not applicable. However, refactoring the\nIO pad data to move this parameter into a separate structure does not\nmake sense because the benefits are marginal.\n\nSupport for the Tegra264 IO pads is currently missing and the control\nfor configuring the voltage for the IO pads for Tegra264 has changed.\nInstead of having a single register that is used for setting the IO pad\nvoltage for all IO pads, there is now a register associated with the\nspecific IO pad. For Tegra264, there is now only one IO pad that can be\nconfigured for 1.8V or 3.3V which is the sdmmc1-hv. While we could make\nthis work with by adding a new SoC flag, the implementation will be a\nbit cumbersome. Therefore, it now seems reasonable to refactor the IO\npad code. Hence, introduce a new 'tegra_io_pad_vctrl' structure that\ncontains the register offset and bit for enabling/disabling 3.3V mode\nand move the existing voltage control data for supported SoCs to this\nstructure. This has an added benefit of simplifying the code in the\nfunctions tegra_io_pad_get_voltage and tegra_io_pad_set_voltage.\n\nSigned-off-by: Jon Hunter <jonathanh@nvidia.com>\n---\n drivers/soc/tegra/pmc.c | 467 ++++++++++++++++++++++------------------\n 1 file changed, 259 insertions(+), 208 deletions(-)", "diff": "diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex 3899d8c76569..3dcc679baffa 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -294,10 +294,15 @@ struct tegra_io_pad_soc {\n \tunsigned int dpd;\n \tunsigned int request;\n \tunsigned int status;\n-\tunsigned int voltage;\n \tconst char *name;\n };\n \n+struct tegra_io_pad_vctrl {\n+\tenum tegra_io_pad id;\n+\tunsigned int offset;\n+\tunsigned int ena_3v3;\n+};\n+\n struct tegra_pmc_regs {\n \tunsigned int scratch0;\n \tunsigned int rst_status;\n@@ -372,6 +377,8 @@ struct tegra_pmc_soc {\n \n \tconst struct tegra_io_pad_soc *io_pads;\n \tunsigned int num_io_pads;\n+\tconst struct tegra_io_pad_vctrl *io_pad_vctrls;\n+\tunsigned int num_io_pad_vctrls;\n \n \tconst struct pinctrl_pin_desc *pin_descs;\n \tunsigned int num_pin_descs;\n@@ -1699,6 +1706,18 @@ tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)\n \treturn NULL;\n }\n \n+static const struct tegra_io_pad_vctrl *\n+tegra_io_pad_vctrl_find(struct tegra_pmc *pmc, enum tegra_io_pad id)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < pmc->soc->num_io_pad_vctrls; i++)\n+\t\tif (pmc->soc->io_pad_vctrls[i].id == id)\n+\t\t\treturn &pmc->soc->io_pad_vctrls[i];\n+\n+\treturn NULL;\n+}\n+\n static int tegra_io_pad_prepare(struct tegra_pmc *pmc,\n \t\t\t\tconst struct tegra_io_pad_soc *pad,\n \t\t\t\tunsigned long *request,\n@@ -1894,43 +1913,30 @@ static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)\n static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,\n \t\t\t\t int voltage)\n {\n-\tconst struct tegra_io_pad_soc *pad;\n+\tconst struct tegra_io_pad_vctrl *pad;\n \tu32 value;\n \n-\tpad = tegra_io_pad_find(pmc, id);\n+\tpad = tegra_io_pad_vctrl_find(pmc, id);\n \tif (!pad)\n \t\treturn -ENOENT;\n \n-\tif (pad->voltage == UINT_MAX)\n-\t\treturn -ENOTSUPP;\n-\n \tmutex_lock(&pmc->powergates_lock);\n \n-\tif (pmc->soc->has_impl_33v_pwr) {\n-\t\tvalue = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);\n-\n-\t\tif (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)\n-\t\t\tvalue &= ~BIT(pad->voltage);\n-\t\telse\n-\t\t\tvalue |= BIT(pad->voltage);\n-\n-\t\ttegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);\n-\t} else {\n-\t\t/* write-enable PMC_PWR_DET_VALUE[pad->voltage] */\n+\tif (!pmc->soc->has_impl_33v_pwr) {\n+\t\t/* write-enable PMC_PWR_DET_VALUE[pad->ena_3v3] */\n \t\tvalue = tegra_pmc_readl(pmc, PMC_PWR_DET);\n-\t\tvalue |= BIT(pad->voltage);\n+\t\tvalue |= BIT(pad->ena_3v3);\n \t\ttegra_pmc_writel(pmc, value, PMC_PWR_DET);\n+\t}\n \n-\t\t/* update I/O voltage */\n-\t\tvalue = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);\n+\tvalue = tegra_pmc_readl(pmc, pad->offset);\n \n-\t\tif (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)\n-\t\t\tvalue &= ~BIT(pad->voltage);\n-\t\telse\n-\t\t\tvalue |= BIT(pad->voltage);\n+\tif (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)\n+\t\tvalue &= ~BIT(pad->ena_3v3);\n+\telse\n+\t\tvalue |= BIT(pad->ena_3v3);\n \n-\t\ttegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);\n-\t}\n+\ttegra_pmc_writel(pmc, value, pad->offset);\n \n \tmutex_unlock(&pmc->powergates_lock);\n \n@@ -1941,22 +1947,16 @@ static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,\n \n static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)\n {\n-\tconst struct tegra_io_pad_soc *pad;\n+\tconst struct tegra_io_pad_vctrl *pad;\n \tu32 value;\n \n-\tpad = tegra_io_pad_find(pmc, id);\n+\tpad = tegra_io_pad_vctrl_find(pmc, id);\n \tif (!pad)\n \t\treturn -ENOENT;\n \n-\tif (pad->voltage == UINT_MAX)\n-\t\treturn -ENOTSUPP;\n+\tvalue = tegra_pmc_readl(pmc, pad->offset);\n \n-\tif (pmc->soc->has_impl_33v_pwr)\n-\t\tvalue = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);\n-\telse\n-\t\tvalue = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);\n-\n-\tif ((value & BIT(pad->voltage)) == 0)\n+\tif ((value & BIT(pad->ena_3v3)) == 0)\n \t\treturn TEGRA_IO_PAD_VOLTAGE_1V8;\n \n \treturn TEGRA_IO_PAD_VOLTAGE_3V3;\n@@ -3710,16 +3710,22 @@ static const u8 tegra124_cpu_powergates[] = {\n \tTEGRA_POWERGATE_CPU3,\n };\n \n-#define TEGRA_IO_PAD(_id, _dpd, _request, _status, _voltage, _name)\t\\\n+#define TEGRA_IO_PAD(_id, _dpd, _request, _status, _name)\t\\\n \t((struct tegra_io_pad_soc) {\t\t\t\t\t\\\n \t\t.id\t\t= (_id),\t\t\t\t\\\n \t\t.dpd\t\t= (_dpd),\t\t\t\t\\\n \t\t.request\t= (_request),\t\t\t\t\\\n \t\t.status\t\t= (_status),\t\t\t\t\\\n-\t\t.voltage\t= (_voltage),\t\t\t\t\\\n \t\t.name\t\t= (_name),\t\t\t\t\\\n \t})\n \n+#define TEGRA_IO_PAD_VCTRL(_id, _offset, _ena_3v3)\t\t\t\\\n+\t((struct tegra_io_pad_vctrl) {\t\t\t\t\t\\\n+\t\t.id\t\t= (_id),\t\t\t\t\\\n+\t\t.offset\t\t= (_offset),\t\t\t\t\\\n+\t\t.ena_3v3\t= (_ena_3v3),\t\t\t\t\\\n+\t})\n+\n #define TEGRA_IO_PIN_DESC(_id, _name)\t\\\n \t((struct pinctrl_pin_desc) {\t\\\n \t\t.number\t= (_id),\t\\\n@@ -3727,36 +3733,36 @@ static const u8 tegra124_cpu_powergates[] = {\n \t})\n \n static const struct tegra_io_pad_soc tegra124_io_pads[] = {\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, UINT_MAX, \"audio\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, UINT_MAX, \"bb\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, UINT_MAX, \"cam\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, UINT_MAX, \"comp\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, \"csia\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, \"csib\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, \"csie\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, \"dsi\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, \"dsib\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, \"dsic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, \"dsid\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, \"hdmi\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, \"hsic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, UINT_MAX, \"hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, \"lvds\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, \"mipi-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, UINT_MAX, \"nand\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, \"pex-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, \"pex-clk1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, \"pex-clk2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, UINT_MAX, \"pex-cntrl\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, UINT_MAX, \"sdmmc1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, UINT_MAX, \"sdmmc3\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, UINT_MAX, \"sdmmc4\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, UINT_MAX, \"sys_ddc\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, UINT_MAX, \"uart\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, \"usb0\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, \"usb1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, \"usb2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, \"usb_bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, \"audio\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_BB, 15, 0x1b8, 0x1bc, \"bb\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, \"cam\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_COMP, 22, 0x1b8, 0x1bc, \"comp\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, \"csia\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, \"csib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, \"csie\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, \"dsi\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, \"dsib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, \"dsic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, \"dsid\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, \"hdmi\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, \"hsic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HV, 6, 0x1c0, 0x1c4, \"hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, \"lvds\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, \"mipi-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_NAND, 13, 0x1b8, 0x1bc, \"nand\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, \"pex-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, \"pex-clk1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, \"pex-clk2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x1c0, 0x1c4, \"pex-cntrl\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, \"sdmmc1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, \"sdmmc3\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 3, 0x1c0, 0x1c4, \"sdmmc4\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SYS_DDC, 26, 0x1c0, 0x1c4, \"sys_ddc\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, \"uart\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, \"usb0\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, \"usb1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, \"usb2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, \"usb_bias\"),\n };\n \n static const struct pinctrl_pin_desc tegra124_pin_descs[] = {\n@@ -3857,46 +3863,60 @@ static const u8 tegra210_cpu_powergates[] = {\n };\n \n static const struct tegra_io_pad_soc tegra210_io_pads[] = {\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, 5, \"audio\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, 18, \"audio-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, 10, \"cam\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, UINT_MAX, \"csia\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, UINT_MAX, \"csib\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, UINT_MAX, \"csic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, UINT_MAX, \"csid\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, UINT_MAX, \"csie\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, UINT_MAX, \"csif\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, 19, \"dbg\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, UINT_MAX, \"debug-nonao\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, 20, \"dmic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, UINT_MAX, \"dp\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, UINT_MAX, \"dsi\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, UINT_MAX, \"dsib\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, UINT_MAX, \"dsic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, UINT_MAX, \"dsid\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, UINT_MAX, \"emmc\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, UINT_MAX, \"emmc2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, 21, \"gpio\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, UINT_MAX, \"hdmi\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, UINT_MAX, \"hsic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, UINT_MAX, \"lvds\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, UINT_MAX, \"mipi-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, UINT_MAX, \"pex-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, UINT_MAX, \"pex-clk1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, UINT_MAX, \"pex-clk2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, 11, \"pex-cntrl\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, 12, \"sdmmc1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, 13, \"sdmmc3\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, 22, \"spi\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, 23, \"spi-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, 2, \"uart\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, UINT_MAX, \"usb0\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, UINT_MAX, \"usb1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, UINT_MAX, \"usb2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, UINT_MAX, \"usb3\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, UINT_MAX, \"usb-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, \"audio\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, \"audio-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, \"cam\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, \"csia\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, \"csib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, \"csic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, \"csid\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, \"csie\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, \"csif\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, \"dbg\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, \"debug-nonao\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, \"dmic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, \"dp\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, \"dsi\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, \"dsib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, \"dsic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, \"dsid\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, \"emmc\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, \"emmc2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, \"gpio\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, \"hdmi\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, \"hsic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, \"lvds\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, \"mipi-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, \"pex-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, \"pex-clk1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, \"pex-clk2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, \"pex-cntrl\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, \"sdmmc1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, \"sdmmc3\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, \"spi\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, \"spi-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, \"uart\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, \"usb0\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, \"usb1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, \"usb2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, \"usb3\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, \"usb-bias\"),\n };\n \n+static const struct tegra_io_pad_vctrl tegra210_io_pad_vctrls[] = {\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO, PMC_PWR_DET_VALUE, 5),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_PWR_DET_VALUE, 18),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_CAM, PMC_PWR_DET_VALUE, 10),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DBG, PMC_PWR_DET_VALUE, 19),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DMIC, PMC_PWR_DET_VALUE, 20),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_GPIO, PMC_PWR_DET_VALUE, 21),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_PEX_CNTRL, PMC_PWR_DET_VALUE, 11),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1, PMC_PWR_DET_VALUE, 12),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3, PMC_PWR_DET_VALUE, 13),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SPI, PMC_PWR_DET_VALUE, 22),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SPI_HV, PMC_PWR_DET_VALUE, 23),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_UART, PMC_PWR_DET_VALUE, 2),\n+};\n static const struct pinctrl_pin_desc tegra210_pin_descs[] = {\n \tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, \"audio\"),\n \tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, \"audio-hv\"),\n@@ -3965,6 +3985,8 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {\n \t.maybe_tz_only = true,\n \t.num_io_pads = ARRAY_SIZE(tegra210_io_pads),\n \t.io_pads = tegra210_io_pads,\n+\t.num_io_pad_vctrls = ARRAY_SIZE(tegra210_io_pad_vctrls),\n+\t.io_pad_vctrls = tegra210_io_pad_vctrls,\n \t.num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),\n \t.pin_descs = tegra210_pin_descs,\n \t.regs = &tegra20_pmc_regs,\n@@ -3987,44 +4009,53 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {\n };\n \n static const struct tegra_io_pad_soc tegra186_io_pads[] = {\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, \"csia\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, \"csib\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, UINT_MAX, \"dsi\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, \"mipi-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, \"pex-clk-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, \"pex-clk3\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, \"pex-clk2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, \"pex-clk1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, UINT_MAX, \"usb0\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, UINT_MAX, \"usb1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, UINT_MAX, \"usb2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, UINT_MAX, \"usb-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, \"uart\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, \"audio\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, UINT_MAX, \"hsic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, \"dbg\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, \"hdmi-dp0\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, \"hdmi-dp1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, \"pex-cntrl\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, 5, \"sdmmc2-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, \"sdmmc4\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, \"cam\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, UINT_MAX, \"dsib\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, UINT_MAX, \"dsic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, UINT_MAX, \"dsid\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, \"csic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, \"csid\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, \"csie\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, \"csif\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, \"spi\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, \"ufs\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, 2, \"dmic-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, \"edp\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, \"sdmmc1-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, \"sdmmc3-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, \"conn\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, \"audio-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, \"ao-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, \"csia\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, \"csib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x74, 0x78, \"dsi\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, \"mipi-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, \"pex-clk-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, \"pex-clk3\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, \"pex-clk2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, \"pex-clk1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x74, 0x78, \"usb0\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x74, 0x78, \"usb1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x74, 0x78, \"usb2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x74, 0x78, \"usb-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, \"uart\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, \"audio\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x74, 0x78, \"hsic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, \"dbg\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, \"hdmi-dp0\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, \"hdmi-dp1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, \"pex-cntrl\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC2_HV, 2, 0x7c, 0x80, \"sdmmc2-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, \"sdmmc4\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, \"cam\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 8, 0x7c, 0x80, \"dsib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 9, 0x7c, 0x80, \"dsic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 10, 0x7c, 0x80, \"dsid\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, \"csic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, \"csid\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, \"csie\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, \"csif\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, \"spi\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, \"ufs\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DMIC_HV, 20, 0x7c, 0x80, \"dmic-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, \"edp\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, \"sdmmc1-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, \"sdmmc3-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, \"conn\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, \"audio-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, \"ao-hv\"),\n+};\n+\n+static const struct tegra_io_pad_vctrl tegra186_io_pad_vctrls[] = {\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC2_HV, PMC_IMPL_E_33V_PWR, 5),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DMIC_HV, PMC_IMPL_E_33V_PWR, 2),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0),\n };\n \n static const struct pinctrl_pin_desc tegra186_pin_descs[] = {\n@@ -4168,6 +4199,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {\n \t.maybe_tz_only = false,\n \t.num_io_pads = ARRAY_SIZE(tegra186_io_pads),\n \t.io_pads = tegra186_io_pads,\n+\t.num_io_pad_vctrls = ARRAY_SIZE(tegra186_io_pad_vctrls),\n+\t.io_pad_vctrls = tegra186_io_pad_vctrls,\n \t.num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),\n \t.pin_descs = tegra186_pin_descs,\n \t.regs = &tegra186_pmc_regs,\n@@ -4192,55 +4225,62 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {\n };\n \n static const struct tegra_io_pad_soc tegra194_io_pads[] = {\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, UINT_MAX, \"csia\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, UINT_MAX, \"csib\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, UINT_MAX, \"mipi-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, UINT_MAX, \"pex-clk-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, UINT_MAX, \"pex-clk3\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, UINT_MAX, \"pex-clk2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, UINT_MAX, \"pex-clk1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, UINT_MAX, \"eqos\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, UINT_MAX, \"pex-clk-2-bias\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, UINT_MAX, \"pex-clk-2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, UINT_MAX, \"dap3\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, UINT_MAX, \"dap5\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, UINT_MAX, \"uart\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, UINT_MAX, \"pwr-ctl\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, UINT_MAX, \"soc-gpio53\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, UINT_MAX, \"audio\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, UINT_MAX, \"gp-pwm2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, UINT_MAX, \"gp-pwm3\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, UINT_MAX, \"soc-gpio12\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, UINT_MAX, \"soc-gpio13\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, UINT_MAX, \"soc-gpio10\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, UINT_MAX, \"uart4\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, UINT_MAX, \"uart5\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, UINT_MAX, \"dbg\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, UINT_MAX, \"hdmi-dp3\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, UINT_MAX, \"hdmi-dp2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, UINT_MAX, \"hdmi-dp0\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, UINT_MAX, \"hdmi-dp1\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, UINT_MAX, \"pex-cntrl\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, UINT_MAX, \"pex-ctl2\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, UINT_MAX, \"pex-l0-rst\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, UINT_MAX, \"pex-l1-rst\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, UINT_MAX, \"sdmmc4\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, UINT_MAX, \"pex-l5-rst\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, UINT_MAX, \"cam\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, UINT_MAX, \"csic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, UINT_MAX, \"csid\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, UINT_MAX, \"csie\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, UINT_MAX, \"csif\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, UINT_MAX, \"spi\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, UINT_MAX, \"ufs\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, UINT_MAX, \"csig\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, UINT_MAX, \"csih\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, UINT_MAX, \"edp\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, 4, \"sdmmc1-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, 6, \"sdmmc3-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, UINT_MAX, \"conn\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, 1, \"audio-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, \"ao-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, \"csia\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, \"csib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x74, 0x78, \"mipi-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, 0x74, 0x78, \"pex-clk-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK3, 5, 0x74, 0x78, \"pex-clk3\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x74, 0x78, \"pex-clk2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 7, 0x74, 0x78, \"pex-clk1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_EQOS, 8, 0x74, 0x78, \"eqos\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, 0x74, 0x78, \"pex-clk-2-bias\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK_2, 10, 0x74, 0x78, \"pex-clk-2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DAP3, 11, 0x74, 0x78, \"dap3\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DAP5, 12, 0x74, 0x78, \"dap5\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x74, 0x78, \"uart\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PWR_CTL, 15, 0x74, 0x78, \"pwr-ctl\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO53, 16, 0x74, 0x78, \"soc-gpio53\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x74, 0x78, \"audio\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM2, 18, 0x74, 0x78, \"gp-pwm2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_GP_PWM3, 19, 0x74, 0x78, \"gp-pwm3\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO12, 20, 0x74, 0x78, \"soc-gpio12\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO13, 21, 0x74, 0x78, \"soc-gpio13\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SOC_GPIO10, 22, 0x74, 0x78, \"soc-gpio10\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART4, 23, 0x74, 0x78, \"uart4\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UART5, 24, 0x74, 0x78, \"uart5\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x74, 0x78, \"dbg\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP3, 26, 0x74, 0x78, \"hdmi-dp3\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP2, 27, 0x74, 0x78, \"hdmi-dp2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 28, 0x74, 0x78, \"hdmi-dp0\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP1, 29, 0x74, 0x78, \"hdmi-dp1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, 0, 0x7c, 0x80, \"pex-cntrl\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CTL2, 1, 0x7c, 0x80, \"pex-ctl2\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L0_RST, 2, 0x7c, 0x80, \"pex-l0-rst\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L1_RST, 3, 0x7c, 0x80, \"pex-l1-rst\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC4, 4, 0x7c, 0x80, \"sdmmc4\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_PEX_L5_RST, 5, 0x7c, 0x80, \"pex-l5-rst\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 6, 0x7c, 0x80, \"cam\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 11, 0x7c, 0x80, \"csic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 12, 0x7c, 0x80, \"csid\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 13, 0x7c, 0x80, \"csie\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 14, 0x7c, 0x80, \"csif\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 15, 0x7c, 0x80, \"spi\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 17, 0x7c, 0x80, \"ufs\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 18, 0x7c, 0x80, \"csig\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 19, 0x7c, 0x80, \"csih\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 21, 0x7c, 0x80, \"edp\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 23, 0x7c, 0x80, \"sdmmc1-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, 24, 0x7c, 0x80, \"sdmmc3-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CONN, 28, 0x7c, 0x80, \"conn\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x7c, 0x80, \"audio-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, \"ao-hv\"),\n+};\n+\n+static const struct tegra_io_pad_vctrl tegra194_io_pad_vctrls[] = {\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0),\n };\n \n static const struct pinctrl_pin_desc tegra194_pin_descs[] = {\n@@ -4363,6 +4403,8 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {\n \t.maybe_tz_only = false,\n \t.num_io_pads = ARRAY_SIZE(tegra194_io_pads),\n \t.io_pads = tegra194_io_pads,\n+\t.num_io_pad_vctrls = ARRAY_SIZE(tegra194_io_pad_vctrls),\n+\t.io_pad_vctrls = tegra194_io_pad_vctrls,\n \t.num_pin_descs = ARRAY_SIZE(tegra194_pin_descs),\n \t.pin_descs = tegra194_pin_descs,\n \t.regs = &tegra194_pmc_regs,\n@@ -4387,21 +4429,28 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {\n };\n \n static const struct tegra_io_pad_soc tegra234_io_pads[] = {\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, UINT_MAX, \"csia\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, UINT_MAX, \"csib\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, UINT_MAX, \"hdmi-dp0\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, UINT_MAX, \"csic\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, UINT_MAX, \"csid\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, UINT_MAX, \"csie\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, UINT_MAX, \"csif\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, UINT_MAX, \"ufs\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, UINT_MAX, \"edp\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, 4, \"sdmmc1-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, 6, \"sdmmc3-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 1, \"audio-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, 0, \"ao-hv\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, UINT_MAX, \"csig\"),\n-\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, UINT_MAX, \"csih\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0xe0c0, 0xe0c4, \"csia\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0xe0c0, 0xe0c4, \"csib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0xe0d0, 0xe0d4, \"hdmi-dp0\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0xe0c0, 0xe0c4, \"csic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0xe0c0, 0xe0c4, \"csid\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0xe0c0, 0xe0c4, \"csie\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0xe0c0, 0xe0c4, \"csif\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 0, 0xe064, 0xe068, \"ufs\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 1, 0xe05c, 0xe060, \"edp\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, 0, 0xe054, 0xe058, \"sdmmc1-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3_HV, UINT_MAX, UINT_MAX, UINT_MAX, \"sdmmc3-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, UINT_MAX, UINT_MAX, UINT_MAX, \"audio-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_AO_HV, UINT_MAX, UINT_MAX, UINT_MAX, \"ao-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0xe0c0, 0xe0c4, \"csig\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0xe0c0, 0xe0c4, \"csih\"),\n+};\n+\n+static const struct tegra_io_pad_vctrl tegra234_io_pad_vctrls[] = {\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_E_33V_PWR, 4),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3_HV, PMC_IMPL_E_33V_PWR, 6),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_IMPL_E_33V_PWR, 1),\n+\tTEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AO_HV, PMC_IMPL_E_33V_PWR, 0),\n };\n \n static const struct pinctrl_pin_desc tegra234_pin_descs[] = {\n@@ -4510,6 +4559,8 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = {\n \t.maybe_tz_only = false,\n \t.num_io_pads = ARRAY_SIZE(tegra234_io_pads),\n \t.io_pads = tegra234_io_pads,\n+\t.num_io_pad_vctrls = ARRAY_SIZE(tegra234_io_pad_vctrls),\n+\t.io_pad_vctrls = tegra234_io_pad_vctrls,\n \t.num_pin_descs = ARRAY_SIZE(tegra234_pin_descs),\n \t.pin_descs = tegra234_pin_descs,\n \t.regs = &tegra234_pmc_regs,\n", "prefixes": [ "08/10" ] }