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GET /api/patches/2216050/?format=api
{ "id": 2216050, "url": "http://patchwork.ozlabs.org/api/patches/2216050/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325184259.366-5-alireza.sanaee@huawei.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325184259.366-5-alireza.sanaee@huawei.com>", "list_archive_url": null, "date": "2026-03-25T18:42:52", "name": "[4/9] hw/cxl: Carry backend metadata in DC extent records", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4026f7aeaac4e232e98b870286ad4fa631cb57bc", "submitter": { "id": 90159, "url": "http://patchwork.ozlabs.org/api/people/90159/?format=api", "name": "Alireza Sanaee", "email": "alireza.sanaee@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260325184259.366-5-alireza.sanaee@huawei.com/mbox/", "series": [ { "id": 497484, "url": "http://patchwork.ozlabs.org/api/series/497484/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497484", "date": "2026-03-25T18:42:48", "name": "Application Specific Tagged Memory Support in CXL Type 3 Devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497484/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216050/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216050/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgwp60lQYz1xy3\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 05:45:34 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w5TEM-0003ti-7a; Wed, 25 Mar 2026 14:45:26 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alireza.sanaee@huawei.com>)\n id 1w5TEK-0003tO-8g\n for qemu-devel@nongnu.org; Wed, 25 Mar 2026 14:45:24 -0400", "from frasgout.his.huawei.com ([185.176.79.56])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alireza.sanaee@huawei.com>)\n id 1w5TEI-000804-00\n for qemu-devel@nongnu.org; Wed, 25 Mar 2026 14:45:23 -0400", "from mail.maildlp.com (unknown [172.18.224.107])\n by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4fgwn86D3YzHnGdQ;\n Thu, 26 Mar 2026 02:44:44 +0800 (CST)", "from dubpeml500005.china.huawei.com (unknown [7.214.145.207])\n by mail.maildlp.com (Postfix) with ESMTPS id ADC8A40587;\n Thu, 26 Mar 2026 02:45:20 +0800 (CST)", "from a2303103017.china.huawei.com (10.47.66.203) by\n dubpeml500005.china.huawei.com (7.214.145.207) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.11; Wed, 25 Mar 2026 18:45:19 +0000" ], "To": "<qemu-devel@nongnu.org>", "CC": "<anisa.su@samsung.com>, <armbru@redhat.com>, <berrange@redhat.com>,\n <eblake@redhat.com>, <jonathan.cameron@huawei.com>,\n <linux-cxl@vger.kernel.org>, <linuxarm@huawei.com>, <lizhijian@fujitsu.com>,\n <mst@redhat.com>, <pbonzini@redhat.com>, <gourry@gourry.net>,\n <nifan.cxl@gmail.com>, <me@linux.beauty>", "Subject": "[PATCH 4/9] hw/cxl: Carry backend metadata in DC extent records", "Date": "Wed, 25 Mar 2026 18:42:52 +0000", "Message-ID": "<20260325184259.366-5-alireza.sanaee@huawei.com>", "X-Mailer": "git-send-email 2.51.0.windows.2", "In-Reply-To": "<20260325184259.366-1-alireza.sanaee@huawei.com>", "References": "<20260325184259.366-1-alireza.sanaee@huawei.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.47.66.203]", "X-ClientProxiedBy": "lhrpeml500011.china.huawei.com (7.191.174.215) To\n dubpeml500005.china.huawei.com (7.214.145.207)", "Received-SPF": "pass client-ip=185.176.79.56;\n envelope-from=alireza.sanaee@huawei.com; helo=frasgout.his.huawei.com", "X-Spam_score_int": "-41", "X-Spam_score": "-4.2", "X-Spam_bar": "----", "X-Spam_report": "(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-to": "Alireza Sanaee <alireza.sanaee@huawei.com>", "From": "Alireza Sanaee via qemu development <qemu-devel@nongnu.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The lazy dc-regions-total-size flow needs more than DPA and length for each\npending or committed extent. Later stages need to remember which backend\nwas selected for the extent, which fixed window owns the mapping, and which\nregion/offset the request came from.\n\nExtend CXLDCExtent and the helper APIs so add, copy, and release paths can\ncarry that metadata alongside the range information. This is preparatory\nplumbing for the patches that map accepted extents into the fixed window\nand tear them down on release.\n\nSigned-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>\n---\n hw/cxl/cxl-mailbox-utils.c | 45 ++++++++++++++++++++++++++-----------\n hw/mem/cxl_type3.c | 23 ++++++++++++++-----\n include/hw/cxl/cxl_device.h | 21 +++++++++++++----\n 3 files changed, 67 insertions(+), 22 deletions(-)", "diff": "diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c\nindex c83b5f90d4..c5427adb3a 100644\n--- a/hw/cxl/cxl-mailbox-utils.c\n+++ b/hw/cxl/cxl-mailbox-utils.c\n@@ -3525,20 +3525,26 @@ CXLDCRegion *cxl_find_dc_region(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len)\n }\n \n void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,\n+ HostMemoryBackend *hm,\n+ struct CXLFixedWindow *fw,\n uint64_t dpa,\n uint64_t len,\n uint8_t *tag,\n- uint16_t shared_seq)\n+ uint16_t shared_seq,\n+ int rid)\n {\n CXLDCExtent *extent;\n \n extent = g_new0(CXLDCExtent, 1);\n+ extent->hm = hm;\n+ extent->fw = fw;\n extent->start_dpa = dpa;\n extent->len = len;\n if (tag) {\n memcpy(extent->tag, tag, 0x10);\n }\n extent->shared_seq = shared_seq;\n+ extent->rid = rid;\n \n QTAILQ_INSERT_TAIL(list, extent, node);\n }\n@@ -3556,17 +3562,21 @@ void cxl_remove_extent_from_extent_list(CXLDCExtentList *list,\n * Return value: the extent group where the extent is inserted.\n */\n CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,\n+ HostMemoryBackend *host_mem,\n+ struct CXLFixedWindow *fw,\n uint64_t dpa,\n uint64_t len,\n uint8_t *tag,\n- uint16_t shared_seq)\n+ uint16_t shared_seq,\n+ int rid)\n {\n if (!group) {\n group = g_new0(CXLDCExtentGroup, 1);\n QTAILQ_INIT(&group->list);\n }\n- cxl_insert_extent_to_extent_list(&group->list, dpa, len,\n- tag, shared_seq);\n+ cxl_insert_extent_to_extent_list(&group->list,\n+ host_mem, fw, dpa, len,\n+ tag, shared_seq, rid);\n return group;\n }\n \n@@ -3747,7 +3757,9 @@ static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,\n dpa = in->updated_entries[i].start_dpa;\n len = in->updated_entries[i].len;\n \n- cxl_insert_extent_to_extent_list(extent_list, dpa, len, NULL, 0);\n+ cxl_insert_extent_to_extent_list(extent_list,\n+ NULL, NULL, dpa, len,\n+ NULL, 0, 0);\n ct3d->dc.total_extent_count += 1;\n ct3d->dc.nr_extents_accepted += 1;\n ct3_set_region_block_backed(ct3d, dpa, len);\n@@ -3774,8 +3786,11 @@ static uint32_t copy_extent_list(CXLDCExtentList *dst,\n }\n \n QTAILQ_FOREACH(ent, src, node) {\n- cxl_insert_extent_to_extent_list(dst, ent->start_dpa, ent->len,\n- ent->tag, ent->shared_seq);\n+ cxl_insert_extent_to_extent_list(dst,\n+ ent->hm, ent->fw,\n+ ent->start_dpa, ent->len,\n+ ent->tag, ent->shared_seq,\n+ ent->rid);\n cnt++;\n }\n return cnt;\n@@ -3830,14 +3845,16 @@ static CXLRetCode cxl_dc_extent_release_dry_run(CXLType3Dev *ct3d,\n \n if (len1) {\n cxl_insert_extent_to_extent_list(updated_list,\n- ent_start_dpa,\n- len1, NULL, 0);\n+ NULL, NULL,\n+ ent_start_dpa, len1,\n+ NULL, 0, ent->rid);\n cnt_delta++;\n }\n if (len2) {\n cxl_insert_extent_to_extent_list(updated_list,\n- dpa + len,\n- len2, NULL, 0);\n+ NULL, NULL,\n+ dpa + len, len2,\n+ NULL, 0, ent->rid);\n cnt_delta++;\n }\n \n@@ -4310,9 +4327,11 @@ static CXLRetCode cmd_fm_initiate_dc_add(const struct cxl_cmd *cmd,\n for (i = 0; i < in->ext_count; i++) {\n CXLDCExtentRaw *ext = &in->extents[i];\n \n- group = cxl_insert_extent_to_extent_group(group, ext->start_dpa,\n+ group = cxl_insert_extent_to_extent_group(group,\n+ NULL, NULL,\n+ ext->start_dpa,\n ext->len, ext->tag,\n- ext->shared_seq);\n+ ext->shared_seq, 0);\n }\n \n cxl_extent_group_list_insert_tail(&ct3d->dc.extents_pending, group);\ndiff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c\nindex 569184975f..bd32532c7a 100644\n--- a/hw/mem/cxl_type3.c\n+++ b/hw/mem/cxl_type3.c\n@@ -2457,11 +2457,24 @@ static void qmp_cxl_process_dynamic_capacity_prescriptive(const char *path,\n memcpy(extents[i].tag, &uuid.data, 0x10);\n extents[i].shared_seq = 0;\n if (type == DC_EVENT_ADD_CAPACITY) {\n- group = cxl_insert_extent_to_extent_group(group,\n- extents[i].start_dpa,\n- extents[i].len,\n- extents[i].tag,\n- extents[i].shared_seq);\n+ if (!dcd->dc.total_capacity_cmd) {\n+ group = cxl_insert_extent_to_extent_group(group,\n+ NULL, NULL,\n+ extents[i].start_dpa,\n+ extents[i].len,\n+ extents[i].tag,\n+ extents[i].shared_seq,\n+ rid);\n+ } else {\n+ group = cxl_insert_extent_to_extent_group(group,\n+ dcd->dc.host_dc,\n+ dcd->dc.fw,\n+ extents[i].start_dpa,\n+ extents[i].len,\n+ extents[i].tag,\n+ extents[i].shared_seq,\n+ rid);\n+ }\n }\n \n list = list->next;\ndiff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h\nindex 630cf44e0e..a84b8ab358 100644\n--- a/include/hw/cxl/cxl_device.h\n+++ b/include/hw/cxl/cxl_device.h\n@@ -10,6 +10,7 @@\n #ifndef CXL_DEVICE_H\n #define CXL_DEVICE_H\n \n+#include \"hw/cxl/cxl.h\"\n #include \"hw/cxl/cxl_component.h\"\n #include \"hw/pci/pci_device.h\"\n #include \"hw/core/register.h\"\n@@ -643,11 +644,14 @@ typedef struct CXLDCExtentRaw {\n } QEMU_PACKED CXLDCExtentRaw;\n \n typedef struct CXLDCExtent {\n+ HostMemoryBackend *hm;\n+ struct CXLFixedWindow *fw;\n uint64_t start_dpa;\n uint64_t len;\n uint8_t tag[0x10];\n uint16_t shared_seq;\n uint8_t rsvd[0x6];\n+ int rid;\n \n QTAILQ_ENTRY(CXLDCExtent) node;\n } CXLDCExtent;\n@@ -780,6 +784,7 @@ struct CXLType3Dev {\n struct dynamic_capacity {\n HostMemoryBackend *host_dc;\n AddressSpace host_dc_as;\n+ struct CXLFixedWindow *fw;\n /*\n * total_capacity is equivalent to the dynamic capability\n * memory region size.\n@@ -854,18 +859,26 @@ CXLDCRegion *cxl_find_dc_region(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len);\n \n void cxl_remove_extent_from_extent_list(CXLDCExtentList *list,\n CXLDCExtent *extent);\n-void cxl_insert_extent_to_extent_list(CXLDCExtentList *list, uint64_t dpa,\n- uint64_t len, uint8_t *tag,\n- uint16_t shared_seq);\n+void cxl_insert_extent_to_extent_list(CXLDCExtentList *list,\n+ HostMemoryBackend *hm,\n+ struct CXLFixedWindow *fw,\n+ uint64_t dpa,\n+ uint64_t len,\n+ uint8_t *tag,\n+ uint16_t shared_seq,\n+ int rid);\n bool test_any_bits_set(const unsigned long *addr, unsigned long nr,\n unsigned long size);\n bool cxl_extents_contains_dpa_range(CXLDCExtentList *list,\n uint64_t dpa, uint64_t len);\n CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group,\n+ HostMemoryBackend *host_mem,\n+ struct CXLFixedWindow *fw,\n uint64_t dpa,\n uint64_t len,\n uint8_t *tag,\n- uint16_t shared_seq);\n+ uint16_t shared_seq,\n+ int rid);\n void cxl_extent_group_list_insert_tail(CXLDCExtentGroupList *list,\n CXLDCExtentGroup *group);\n uint32_t cxl_extent_group_list_delete_front(CXLDCExtentGroupList *list);\n", "prefixes": [ "4/9" ] }