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GET /api/patches/2215882/?format=api
{ "id": 2215882, "url": "http://patchwork.ozlabs.org/api/patches/2215882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325135811.148480-4-jonathanh@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325135811.148480-4-jonathanh@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T13:58:11", "name": "[V3,3/3] arm64: tegra: Fix Tegra234 MGBE PTP clock", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "650bdc933d3a8ce4a3d6c7e41d93399c02e4c6cd", "submitter": { "id": 66273, "url": "http://patchwork.ozlabs.org/api/people/66273/?format=api", "name": "Jon Hunter", "email": "jonathanh@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325135811.148480-4-jonathanh@nvidia.com/mbox/", "series": [ { "id": 497451, "url": "http://patchwork.ozlabs.org/api/series/497451/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497451", "date": "2026-03-25T13:58:11", "name": "net: stmmac: Fix Tegra234 MGBE clock", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497451/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215882/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215882/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13233-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=pL54892V;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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pr=C", "From": "Jon Hunter <jonathanh@nvidia.com>", "To": "Andrew Lunn <andrew+netdev@lunn.ch>, \"David S . Miller\"\n\t<davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, Jakub Kicinski\n\t<kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>", "CC": "<netdev@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, Jon Hunter <jonathanh@nvidia.com>", "Subject": "[PATCH V3 3/3] arm64: tegra: Fix Tegra234 MGBE PTP clock", "Date": "Wed, 25 Mar 2026 13:58:11 +0000", "Message-ID": "<20260325135811.148480-4-jonathanh@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260325135811.148480-1-jonathanh@nvidia.com>", "References": "<20260325135811.148480-1-jonathanh@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": 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"\n\tA6aaIUm5v3NRTKaGqtOJ3LLFkijGQutcIzTtlAiV9GD8sR0CmGcrcN/e9NeIpAPZ2P/gWyOlJMtbq1W5CSBTyPWFFNy7iFbt9yH+17pIGCZz153z7mhyiI1fZuxKWCq+/NwqAu/lGnYdEyXjtEcG9b3kISXFqEDvks4I0WiGhESSGYz2GEyahuoHCje8MPVM6O6kya81Aqmwt9WxDK0zXyaMJftKrSB3JWwJORUBIKYZhTLnnP8+1e2qB/6HDSkYjgfgKb2cd1hgSRB8KuRmSt4YuStrCt+KUnnU8cc/Qr+3qlPkuHnnxcSUuE5ql2GeJcXKwwt+h85/yhRS/U/vqHCuwDOsyQ4R9sOnI0T9dTfLRFk6vJGN/hzouS/UPuUFG80WlpBJ2Y6wBY0/VjPNwov0u2RkC+MNFbeHnbFZOzU9UVaoKLCfm1QVrFcjXnB/c3R77kQHeYggOWIkVfNMj54JsdxrYhR20bAlFGEOUSMFFohf+tm7mjO5TnHtK+cIi9mOPW64P9yvgCGHpF4uGoIkVKKVkgtJQ0PSQbVXFO3URPewmbkKboJcetNYQh4mmJXZ0tNID4cO8bwg0m/MbcdckiV26+QnJ3ux2tptlkGO3LcNBZVDyoYuOXROCqHUHGJePgXt+EiLeEcGR31Hp5D4D55dJWoM/Y1lXFx/T1FnlxGP1rMsskMf0fZdzpM0b2TnDkQsuMn5E9B0Pui9IbbuoQg1Mesd7TrCxtIPE4Oq66q9XbRzNqoEb/Za+SabcU9z3d12pspozziejA3M+A==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(82310400026)(376014)(7416014)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\taRVaUmjw/AXSvkpOoARqrtKgbAeLDbULG3eK9RUUISkyqjYUnZwPkUsoQ4xaqBvDJDPy8++IlcVMMwDUB5pZiDAoSNiUZNDil+IZUIkNWk0WU3iOLvVeAID7QoB1tsx4gh1TQRmsHwgaIP8cbDezUXufD0d00zIpkZ6xB8u6uik/s61au6TdSYeK3qAEL1qOee+BBXjCRQwGaDYYKTQfXUGB2qkjBk58/otNl6iM4+v3Bbwwq2DkWvgdT7WQ4A/9dgsE3yFo0r7F1IG7Ny9BI0qx5VSjBk6pj/ipaFG6N1UW7TzuHcQKWlra9kpdcCKlzs0ujzHEqJlovhk0z2gYoeDZ+LysXHtoEXT4Wx5ztuvJCwMHMXfi9WJW+SSF2trSggjzYqE1YHssi+sWe7k1SQ4KHz7zAztWZP7gPjInFMvv15dfIMr3/3+bOxOqs5Pg", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 13:59:01.6378\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 97fe5123-85ba-4872-725e-08de8a76ab48", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCY4PEPF0000EE38.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB5954" }, "content": "The Tegra MGBE PTP clock is incorrectly named as 'ptp-ref' and not\n'ptp_ref' and this causing the initialisation of the PTP clock to fail.\nThe device-tree binding doc for the device and the Tegra MGBE driver\nhave been updated to use the correct name and so update the device-tree\nfor Tegra234 as well.\n\nFixes: 610cdf3186bc (\"arm64: tegra: Add MGBE nodes on Tegra234\")\nSigned-off-by: Jon Hunter <jonathanh@nvidia.com>\n---\n arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)", "diff": "diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi\nindex 04a95b6658ca..18220cdac9f9 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi\n@@ -3605,7 +3605,7 @@ ethernet@6800000 {\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;\n-\t\t\tclock-names = \"mgbe\", \"mac\", \"mac-divider\", \"ptp-ref\", \"rx-input-m\",\n+\t\t\tclock-names = \"mgbe\", \"mac\", \"mac-divider\", \"ptp_ref\", \"rx-input-m\",\n \t\t\t\t \"rx-input\", \"tx\", \"eee-pcs\", \"rx-pcs-input\", \"rx-pcs-m\",\n \t\t\t\t \"rx-pcs\", \"tx-pcs\";\n \t\t\tresets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,\n@@ -3647,7 +3647,7 @@ ethernet@6900000 {\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;\n-\t\t\tclock-names = \"mgbe\", \"mac\", \"mac-divider\", \"ptp-ref\", \"rx-input-m\",\n+\t\t\tclock-names = \"mgbe\", \"mac\", \"mac-divider\", \"ptp_ref\", \"rx-input-m\",\n \t\t\t\t \"rx-input\", \"tx\", \"eee-pcs\", \"rx-pcs-input\", \"rx-pcs-m\",\n \t\t\t\t \"rx-pcs\", \"tx-pcs\";\n \t\t\tresets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,\n@@ -3689,7 +3689,7 @@ ethernet@6a00000 {\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;\n-\t\t\tclock-names = \"mgbe\", \"mac\", \"mac-divider\", \"ptp-ref\", \"rx-input-m\",\n+\t\t\tclock-names = \"mgbe\", \"mac\", \"mac-divider\", \"ptp_ref\", \"rx-input-m\",\n \t\t\t\t \"rx-input\", \"tx\", \"eee-pcs\", \"rx-pcs-input\", \"rx-pcs-m\",\n \t\t\t\t \"rx-pcs\", \"tx-pcs\";\n \t\t\tresets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,\n@@ -3731,7 +3731,7 @@ ethernet@6b00000 {\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,\n \t\t\t\t <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;\n-\t\t\tclock-names = \"mgbe\", \"mac\", \"mac-divider\", \"ptp-ref\", \"rx-input-m\",\n+\t\t\tclock-names = \"mgbe\", \"mac\", \"mac-divider\", \"ptp_ref\", \"rx-input-m\",\n \t\t\t\t \"rx-input\", \"tx\", \"eee-pcs\", \"rx-pcs-input\", \"rx-pcs-m\",\n \t\t\t\t \"rx-pcs\", \"tx-pcs\";\n \t\t\tresets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,\n", "prefixes": [ "V3", "3/3" ] }