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GET /api/patches/2215841/?format=api
{ "id": 2215841, "url": "http://patchwork.ozlabs.org/api/patches/2215841/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325125726.2694144-3-sumitg@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325125726.2694144-3-sumitg@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T12:57:26", "name": "[v2,2/2] soc/tegra: cbb: Add support for CBB fabrics in Tegra238", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "fbd5bee7f463b6baf4107e3015f8a982f23e1e79", "submitter": { "id": 69778, "url": "http://patchwork.ozlabs.org/api/people/69778/?format=api", "name": "Sumit Gupta", "email": "sumitg@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325125726.2694144-3-sumitg@nvidia.com/mbox/", "series": [ { "id": 497438, "url": "http://patchwork.ozlabs.org/api/series/497438/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497438", "date": "2026-03-25T12:57:25", "name": "soc/tegra: cbb: Add Tegra238 support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497438/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215841/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215841/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13217-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Sumit Gupta <sumitg@nvidia.com>", "To": "<treding@nvidia.com>, <jonathanh@nvidia.com>, <robh@kernel.org>,\n\t<krzk+dt@kernel.org>, <conor+dt@kernel.org>", "CC": "<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <bbasu@nvidia.com>, <sumitg@nvidia.com>", "Subject": "[PATCH v2 2/2] soc/tegra: cbb: Add support for CBB fabrics in\n Tegra238", "Date": "Wed, 25 Mar 2026 18:27:26 +0530", "Message-ID": "<20260325125726.2694144-3-sumitg@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260325125726.2694144-1-sumitg@nvidia.com>", "References": "<20260325125726.2694144-1-sumitg@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": 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"\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tBq9wPd76WCs5/7y765ZINerrZalVCMLVLhOot1CGKBPtIdOLWYTvWMVgxlM6zsQcgIYoq0Ke+Ep5PQqX//Z/HKQSSoQVwUgvV4Aodw5rvnL6ni98PrP+Y915lswtGbJSc6y3UmjBJfr4x6ainaTACH47YyVrqyF6xBBqPcxCjH26HMVFA5wEOZc/4hTI2teMM0eDxdW/tfg0fQBTXthN+GZwsyw9F3I91UMPUY6WxjV6yvUfaiFq2l725k1Fyld9vJ+UlcaJ9LJ0PQrDq+0R506Cxpp132RM4mfo++8RRwJTz49rTRD2lR+X6sgYyb8vIJPUc3khdPUksIsB9dHoVFsY4EFoKPAbZygByIRGjGt7fJXy3RvaFEP0/qwYx16w5QwWUGvGUrPagsIx/Dpo+6WKTs0ddT2c+4Oj2B4FhQne/zukfMxGBZjR+si63duv", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 12:58:01.9873\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 22ac1dfb-972e-4bed-2d2e-08de8a6e25ff", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF0001A0FB.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB7637" }, "content": "Add support for CBB 2.0 based fabrics in Tegra238 SoC using DT.\nFabrics reporting errors are: CBB, AON, BPMP, APE.\n\nSigned-off-by: Sumit Gupta <sumitg@nvidia.com>\n---\n drivers/soc/tegra/cbb/tegra234-cbb.c | 134 +++++++++++++++++++++++++++\n 1 file changed, 134 insertions(+)", "diff": "diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c\nindex a9adbcecd47c..30f421c8e90c 100644\n--- a/drivers/soc/tegra/cbb/tegra234-cbb.c\n+++ b/drivers/soc/tegra/cbb/tegra234-cbb.c\n@@ -89,6 +89,15 @@ enum tegra234_cbb_fabric_ids {\n \tT234_MAX_FABRIC_ID,\n };\n \n+enum tegra238_cbb_fabric_ids {\n+\tT238_CBB_FABRIC_ID = 0,\n+\tT238_AON_FABRIC_ID = 4,\n+\tT238_PSC_FABRIC_ID = 5,\n+\tT238_BPMP_FABRIC_ID = 6,\n+\tT238_APE_FABRIC_ID = 7,\n+\tT238_MAX_FABRIC_ID,\n+};\n+\n enum tegra264_cbb_fabric_ids {\n \tT264_SYSTEM_CBB_FABRIC_ID,\n \tT264_TOP_0_CBB_FABRIC_ID,\n@@ -974,6 +983,127 @@ static const struct tegra234_cbb_fabric tegra234_sce_fabric = {\n \t.firewall_wr_ctl = 0x288,\n };\n \n+static const struct tegra234_target_lookup tegra238_ape_target_map[] = {\n+\t{ \"AXI2APB\", 0x00000 },\n+\t{ \"AGIC\", 0x15000 },\n+\t{ \"AMC\", 0x16000 },\n+\t{ \"AST0\", 0x17000 },\n+\t{ \"AST1\", 0x18000 },\n+\t{ \"AST2\", 0x19000 },\n+\t{ \"CBB\", 0x1A000 },\n+};\n+\n+static const struct tegra234_target_lookup tegra238_cbb_target_map[] = {\n+\t{ \"AON\", 0x40000 },\n+\t{ \"APE\", 0x50000 },\n+\t{ \"BPMP\", 0x41000 },\n+\t{ \"HOST1X\", 0x43000 },\n+\t{ \"STM\", 0x44000 },\n+\t{ \"CBB_CENTRAL\", 0x00000 },\n+\t{ \"PCIE_C0\", 0x51000 },\n+\t{ \"PCIE_C1\", 0x47000 },\n+\t{ \"PCIE_C2\", 0x48000 },\n+\t{ \"PCIE_C3\", 0x49000 },\n+\t{ \"GPU\", 0x4C000 },\n+\t{ \"SMMU0\", 0x4D000 },\n+\t{ \"SMMU1\", 0x4E000 },\n+\t{ \"SMMU2\", 0x4F000 },\n+\t{ \"PSC\", 0x52000 },\n+\t{ \"AXI2APB_1\", 0x70000 },\n+\t{ \"AXI2APB_12\", 0x73000 },\n+\t{ \"AXI2APB_13\", 0x74000 },\n+\t{ \"AXI2APB_15\", 0x76000 },\n+\t{ \"AXI2APB_16\", 0x77000 },\n+\t{ \"AXI2APB_18\", 0x79000 },\n+\t{ \"AXI2APB_19\", 0x7A000 },\n+\t{ \"AXI2APB_2\", 0x7B000 },\n+\t{ \"AXI2APB_23\", 0x7F000 },\n+\t{ \"AXI2APB_25\", 0x80000 },\n+\t{ \"AXI2APB_26\", 0x81000 },\n+\t{ \"AXI2APB_27\", 0x82000 },\n+\t{ \"AXI2APB_28\", 0x83000 },\n+\t{ \"AXI2APB_32\", 0x87000 },\n+\t{ \"AXI2APB_33\", 0x88000 },\n+\t{ \"AXI2APB_4\", 0x8B000 },\n+\t{ \"AXI2APB_5\", 0x8C000 },\n+\t{ \"AXI2APB_6\", 0x93000 },\n+\t{ \"AXI2APB_9\", 0x90000 },\n+\t{ \"AXI2APB_3\", 0x91000 },\n+};\n+\n+static const struct tegra234_fabric_lookup tegra238_cbb_fab_list[] = {\n+\t[T238_CBB_FABRIC_ID] = { \"cbb-fabric\", true,\n+\t\t\t\t tegra238_cbb_target_map,\n+\t\t\t\t ARRAY_SIZE(tegra238_cbb_target_map) },\n+\t[T238_AON_FABRIC_ID] = { \"aon-fabric\", true,\n+\t\t\t\t tegra234_aon_target_map,\n+\t\t\t\t ARRAY_SIZE(tegra234_aon_target_map) },\n+\t[T238_PSC_FABRIC_ID] = { \"psc-fabric\" },\n+\t[T238_BPMP_FABRIC_ID] = { \"bpmp-fabric\", true,\n+\t\t\t\t tegra234_bpmp_target_map,\n+\t\t\t\t ARRAY_SIZE(tegra234_bpmp_target_map) },\n+\t[T238_APE_FABRIC_ID] = { \"ape-fabric\", true,\n+\t\t\t\t tegra238_ape_target_map,\n+\t\t\t\t ARRAY_SIZE(tegra238_ape_target_map) },\n+};\n+\n+static const struct tegra234_cbb_fabric tegra238_aon_fabric = {\n+\t.fab_id = T238_AON_FABRIC_ID,\n+\t.fab_list = tegra238_cbb_fab_list,\n+\t.initiator_id = tegra234_initiator_id,\n+\t.errors = tegra234_cbb_errors,\n+\t.max_errors = ARRAY_SIZE(tegra234_cbb_errors),\n+\t.err_intr_enbl = 0x7,\n+\t.err_status_clr = 0x3f,\n+\t.notifier_offset = 0x17000,\n+\t.firewall_base = 0x30000,\n+\t.firewall_ctl = 0x8f0,\n+\t.firewall_wr_ctl = 0x8e8,\n+};\n+\n+static const struct tegra234_cbb_fabric tegra238_ape_fabric = {\n+\t.fab_id = T238_APE_FABRIC_ID,\n+\t.fab_list = tegra238_cbb_fab_list,\n+\t.initiator_id = tegra234_initiator_id,\n+\t.errors = tegra234_cbb_errors,\n+\t.max_errors = ARRAY_SIZE(tegra234_cbb_errors),\n+\t.err_intr_enbl = 0xf,\n+\t.err_status_clr = 0x3f,\n+\t.notifier_offset = 0x1E000,\n+\t.firewall_base = 0x30000,\n+\t.firewall_ctl = 0xad0,\n+\t.firewall_wr_ctl = 0xac8,\n+};\n+\n+static const struct tegra234_cbb_fabric tegra238_bpmp_fabric = {\n+\t.fab_id = T238_BPMP_FABRIC_ID,\n+\t.fab_list = tegra238_cbb_fab_list,\n+\t.initiator_id = tegra234_initiator_id,\n+\t.errors = tegra234_cbb_errors,\n+\t.max_errors = ARRAY_SIZE(tegra234_cbb_errors),\n+\t.err_intr_enbl = 0xf,\n+\t.err_status_clr = 0x3f,\n+\t.notifier_offset = 0x19000,\n+\t.firewall_base = 0x30000,\n+\t.firewall_ctl = 0x8f0,\n+\t.firewall_wr_ctl = 0x8e8,\n+};\n+\n+static const struct tegra234_cbb_fabric tegra238_cbb_fabric = {\n+\t.fab_id = T238_CBB_FABRIC_ID,\n+\t.fab_list = tegra238_cbb_fab_list,\n+\t.initiator_id = tegra234_initiator_id,\n+\t.errors = tegra234_cbb_errors,\n+\t.max_errors = ARRAY_SIZE(tegra234_cbb_errors),\n+\t.err_intr_enbl = 0x3f,\n+\t.err_status_clr = 0x3f,\n+\t.notifier_offset = 0x60000,\n+\t.off_mask_erd = 0x3d004,\n+\t.firewall_base = 0x10000,\n+\t.firewall_ctl = 0x2230,\n+\t.firewall_wr_ctl = 0x2228,\n+};\n+\n static const char * const tegra241_initiator_id[] = {\n \t[0x0] = \"TZ\",\n \t[0x1] = \"CCPLEX\",\n@@ -1480,6 +1610,10 @@ static const struct of_device_id tegra234_cbb_dt_ids[] = {\n \t{ .compatible = \"nvidia,tegra234-dce-fabric\", .data = &tegra234_dce_fabric },\n \t{ .compatible = \"nvidia,tegra234-rce-fabric\", .data = &tegra234_rce_fabric },\n \t{ .compatible = \"nvidia,tegra234-sce-fabric\", .data = &tegra234_sce_fabric },\n+\t{ .compatible = \"nvidia,tegra238-aon-fabric\", .data = &tegra238_aon_fabric },\n+\t{ .compatible = \"nvidia,tegra238-ape-fabric\", .data = &tegra238_ape_fabric },\n+\t{ .compatible = \"nvidia,tegra238-bpmp-fabric\", .data = &tegra238_bpmp_fabric },\n+\t{ .compatible = \"nvidia,tegra238-cbb-fabric\", .data = &tegra238_cbb_fabric },\n \t{ .compatible = \"nvidia,tegra264-sys-cbb-fabric\", .data = &tegra264_sys_cbb_fabric },\n \t{ .compatible = \"nvidia,tegra264-top0-cbb-fabric\", .data = &tegra264_top0_cbb_fabric },\n \t{ .compatible = \"nvidia,tegra264-uphy0-cbb-fabric\", .data = &tegra264_uphy0_cbb_fabric },\n", "prefixes": [ "v2", "2/2" ] }