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GET /api/patches/2215788/?format=api
{ "id": 2215788, "url": "http://patchwork.ozlabs.org/api/patches/2215788/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325-t264-pwm-v2-7-998d885984b3@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325-t264-pwm-v2-7-998d885984b3@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T10:17:05", "name": "[v2,7/7] arm64: tegra: Add PWM controllers on Tegra264", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "693c4a9359127c4ba47e096aa76a1e41da82f3a9", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325-t264-pwm-v2-7-998d885984b3@nvidia.com/mbox/", "series": [ { "id": 497411, "url": "http://patchwork.ozlabs.org/api/series/497411/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497411", "date": "2026-03-25T10:16:58", "name": "Tegra264 PWM support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497411/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215788/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215788/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13205-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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"In-Reply-To": "<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Thierry Reding <treding@nvidia.com>,\n Mikko Perttunen <mperttunen@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "TP0P295CA0002.TWNP295.PROD.OUTLOOK.COM\n (2603:1096:910:2::15) To SJ2PR12MB9161.namprd12.prod.outlook.com\n (2603:10b6:a03:566::20)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", 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"X-MS-Exchange-AntiSpam-MessageData-1": "H9IXf5czcbskRg==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a913edb5-56e8-4d89-858f-08de8a57cff9", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 10:18:09.1678\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n gcUReNsTV5SGfjHjpjag/mtpW+CQWGuxX9qcLy7qKCgwG/mha+pK+gAJUmGrTTNiZhsZoWDtRi0nk992Loxa8A==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS5PPFA3734E4BA" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nTegra264 has a number of PWM controller which are similar to those found\non earlier chips but with some added functionality.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 72 ++++++++++++++++++++++++++++++++\n 1 file changed, 72 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\nindex 7644a41d5f72..13fd04068016 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n@@ -3336,6 +3336,18 @@ i2c3: i2c@c610000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm4: pwm@c6a0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc6a0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM4>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM4>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n \t\tpmc: pmc@c800000 {\n \t\t\tcompatible = \"nvidia,tegra264-pmc\";\n \t\t\treg = <0x0 0x0c800000 0x0 0x100000>,\n@@ -3538,6 +3550,66 @@ i2c16: i2c@c430000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpwm2: pwm@c5e0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc5e0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM2>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM2>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm3: pwm@c5f0000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc5f0000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM3>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM3>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm5: pwm@c600000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc600000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM5>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM5>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm9: pwm@c610000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc610000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM9>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM9>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n+\t\tpwm10: pwm@c620000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pwm\";\n+\t\t\treg = <0x0 0xc620000 0x0 0x10000>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tclocks = <&bpmp TEGRA264_CLK_PWM10>;\n+\t\t\tresets = <&bpmp TEGRA264_RESET_PWM10>;\n+\t\t\treset-names = \"pwm\";\n+\n+\t\t\t#pwm-cells = <2>;\n+\t\t};\n+\n \t\ti2c0: i2c@c630000 {\n \t\t\tcompatible = \"nvidia,tegra264-i2c\";\n \t\t\treg = <0x00 0x0c630000 0x0 0x10000>;\n", "prefixes": [ "v2", "7/7" ] }