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GET /api/patches/2215784/?format=api
{ "id": 2215784, "url": "http://patchwork.ozlabs.org/api/patches/2215784/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325-t264-pwm-v2-5-998d885984b3@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325-t264-pwm-v2-5-998d885984b3@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T10:17:03", "name": "[v2,5/7] pwm: tegra: Parametrize duty and scale field widths", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "59207791330660d6302f445b2883b780407bacb6", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325-t264-pwm-v2-5-998d885984b3@nvidia.com/mbox/", "series": [ { "id": 497411, "url": "http://patchwork.ozlabs.org/api/series/497411/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497411", "date": "2026-03-25T10:16:58", "name": "Tegra264 PWM support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497411/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215784/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215784/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13203-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=yWTuFH2ku7rYybzhP0qo9F0sgEx2rGXM3tRrGkq4dlo=;\n b=PY0l9WUtCUbiZRpdOS3a4dGMHhM/XBlaJEJF7rBUmYJGkrRfvgUFBGId4KAsx4fWEHRjdn4j2Zc8oIrXnsG0UZCksy/ThKT3b94HMi4wvfZ6mdHneY4t6hICBzP5g4WDgxqsrjWE/hO1aaCsRJMVpqwQ2ehew4d6oZ6JafxC/ZfFUYxSzqQ8WPXGXqWO6yLCJ4HwnJ129NDPnGOWvT8ZcTKmXe2WEuEvanYQflT0b1Zt67/QUG2BVACQ7Y1zuBcoWIjuT3ruOi+Yf56QELQrEep6V/KPVOW2P2PwE4Y+9S/A3M7IwCxIpNlH5R95q/q5BN2uIqbhLG1lu/7e3JkL/g==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Wed, 25 Mar 2026 19:17:03 +0900", "Subject": "[PATCH v2 5/7] pwm: tegra: Parametrize duty and scale field widths", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260325-t264-pwm-v2-5-998d885984b3@nvidia.com>", "References": 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"X-MS-Exchange-AntiSpam-MessageData-1": "Jc306IebehhoNKJEyRcTz8UJADtkvWpfe9E=", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 08496e34-edb6-4f91-d893-08de8a57ca93", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 10:18:00.1680\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n Qs+WwcOnN/VUFfVZ9qJkV+z4zlPz8R9HrU8PICroB+X1z2KJWFnkL2L4itpjHcq0O0xmPdEs5VgIvYJ3dqBuqQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS5PPFA3734E4BA" }, "content": "Tegra264 has wider fields for the duty and scale register fields.\nParameterize the driver in preparation. The depth value also\nbecomes disconnected from the width of the duty field, so define\nit separately.\n\nCo-developed-by: Yi-Wei Wang <yiweiw@nvidia.com>\nSigned-off-by: Yi-Wei Wang <yiweiw@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/pwm/pwm-tegra.c | 29 ++++++++++++++++++-----------\n 1 file changed, 18 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 22d709986e8c..857301baad51 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -52,16 +52,19 @@\n #include <soc/tegra/common.h>\n \n #define PWM_ENABLE\t(1 << 31)\n-#define PWM_DUTY_WIDTH\t8\n #define PWM_DUTY_SHIFT\t16\n-#define PWM_SCALE_WIDTH\t13\n #define PWM_SCALE_SHIFT\t0\n \n #define PWM_CSR_0\t0\n \n+#define PWM_DEPTH\t256\n+\n struct tegra_pwm_soc {\n \tunsigned int num_channels;\n \tunsigned int enable_reg;\n+\n+\tunsigned int duty_width;\n+\tunsigned int scale_width;\n };\n \n struct tegra_pwm_chip {\n@@ -106,22 +109,22 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \n \t/*\n \t * Convert from duty_ns / period_ns to a fixed number of duty ticks\n-\t * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the\n+\t * per PWM_DEPTH cycles and make sure to round to the\n \t * nearest integer during division.\n \t */\n-\tc *= (1 << PWM_DUTY_WIDTH);\n+\tc *= PWM_DEPTH;\n \tc = DIV_ROUND_CLOSEST_ULL(c, period_ns);\n \n \tval = (u32)c << PWM_DUTY_SHIFT;\n \n \t/*\n-\t * min period = max clock limit >> PWM_DUTY_WIDTH\n+\t * min period = max clock limit / PWM_DEPTH\n \t */\n \tif (period_ns < pc->min_period_ns)\n \t\treturn -EINVAL;\n \n \t/*\n-\t * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)\n+\t * Compute the prescaler value for which PWM_DEPTH\n \t * cycles at the PWM clock rate will take period_ns nanoseconds.\n \t *\n \t * num_channels: If single instance of PWM controller has multiple\n@@ -135,7 +138,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t */\n \tif (pc->soc->num_channels == 1) {\n \t\t/*\n-\t\t * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches\n+\t\t * Rate is multiplied with PWM_DEPTH so that it matches\n \t\t * with the maximum possible rate that the controller can\n \t\t * provide. Any further lower value can be derived by setting\n \t\t * PFM bits[0:12].\n@@ -145,7 +148,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t\t * source clock rate as required_clk_rate, PWM controller will\n \t\t * be able to configure the requested period.\n \t\t */\n-\t\trequired_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,\n+\t\trequired_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * PWM_DEPTH,\n \t\t\t\t\t\t period_ns);\n \n \t\tif (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))\n@@ -169,7 +172,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \n \t/* Consider precision in PWM_SCALE_WIDTH rate calculation */\n \trate = mul_u64_u64_div_u64(pc->clk_rate, period_ns,\n-\t\t\t\t (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH);\n+\t\t\t\t (u64)NSEC_PER_SEC * PWM_DEPTH);\n \n \t/*\n \t * Since the actual PWM divider is the register's frequency divider\n@@ -185,7 +188,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,\n \t * Make sure that the rate will fit in the register's frequency\n \t * divider field.\n \t */\n-\tif (rate >> PWM_SCALE_WIDTH)\n+\tif (rate >> pc->soc->scale_width)\n \t\treturn -EINVAL;\n \n \tval |= rate << PWM_SCALE_SHIFT;\n@@ -324,7 +327,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)\n \n \t/* Set minimum limit of PWM period for the IP */\n \tpc->min_period_ns =\n-\t (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1;\n+\t (NSEC_PER_SEC / (pc->clk_rate / PWM_DEPTH)) + 1;\n \n \tpc->rst = devm_reset_control_get_exclusive(&pdev->dev, \"pwm\");\n \tif (IS_ERR(pc->rst)) {\n@@ -404,11 +407,15 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)\n static const struct tegra_pwm_soc tegra20_pwm_soc = {\n \t.num_channels = 4,\n \t.enable_reg = PWM_CSR_0,\n+\t.duty_width = 8,\n+\t.scale_width = 13,\n };\n \n static const struct tegra_pwm_soc tegra186_pwm_soc = {\n \t.num_channels = 1,\n \t.enable_reg = PWM_CSR_0,\n+\t.duty_width = 8,\n+\t.scale_width = 13,\n };\n \n static const struct of_device_id tegra_pwm_of_match[] = {\n", "prefixes": [ "v2", "5/7" ] }