Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2215783/?format=api
{ "id": 2215783, "url": "http://patchwork.ozlabs.org/api/patches/2215783/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325-t264-pwm-v2-2-998d885984b3@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325-t264-pwm-v2-2-998d885984b3@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T10:17:00", "name": "[v2,2/7] pwm: tegra: Avoid hard-coded max clock frequency", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "579bcd179eb413e94911aaa03823622c6c8eebf5", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325-t264-pwm-v2-2-998d885984b3@nvidia.com/mbox/", "series": [ { "id": 497411, "url": "http://patchwork.ozlabs.org/api/series/497411/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497411", "date": "2026-03-25T10:16:58", "name": "Tegra264 PWM support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497411/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215783/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215783/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13200-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=TNHGT6uo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-13200-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"TNHGT6uo\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.93.194.22", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com", "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=nvidia.com;" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgjgd4S8xz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 21:24:13 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 210D13162CD8\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 10:17:54 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E336E3B5820;\n\tWed, 25 Mar 2026 10:17:53 +0000 (UTC)", "from SN4PR0501CU005.outbound.protection.outlook.com\n (mail-southcentralusazon11011022.outbound.protection.outlook.com\n [40.93.194.22])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id CC3F63ACF17;\n\tWed, 25 Mar 2026 10:17:51 +0000 (UTC)", "from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20)\n by DS5PPFA3734E4BA.namprd12.prod.outlook.com (2603:10b6:f:fc00::65c) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.20; Wed, 25 Mar\n 2026 10:17:46 +0000", "from SJ2PR12MB9161.namprd12.prod.outlook.com\n ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com\n ([fe80::d9d1:8c49:a703:b017%4]) with mapi id 15.20.9745.019; Wed, 25 Mar 2026\n 10:17:46 +0000" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774433873; cv=fail;\n b=J0byu7ky/bRurDw4LK29vqnBKwqIo9TILVbHyJEpsEgSLjOXNr+hVxTbyntl6rpV0tUsynHL9ngGns86shKp77V72yDPWO3e0hMB80iC2Q2WqTn42TzUMM+qJU353XNJG5DHS+h+wImoFfdgG0/RZ1XzVPXOTewTfIAPwMQPvKA=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=ycXFcyUwAGsPkcWJDA4zbrp0CggHt1045UobuGLOiIAnDLC/YxEogw+q1fWYCZ6FWT9LS4pzA/5yzYlz9XIMash46uCLN50CLTXgogcUuq3m18mFasyGyNc7HKYJ3c6hGBjaSJFaFdhbbd4VxyhKLqUwNYe/rHarbOu1sz1V+M+9OPH559ArkTQYUQWkohZi9VExUJMDhvOPIMrh5pEu48bhOL0iNgBVOyi69g1wfOa8Pqk9HG5zZ30UhYj3rZlsnaAxbg8BAF56i1LiWI/X1J+oFc1HL4tRfyyIwmTz97cGRytAc7ZpkIA3Po2InKj7wdANF8oDIcspp7miVILiUQ==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774433873; c=relaxed/simple;\n\tbh=gwfZQNWBWxoyNzQ8CFlQALVbozDu4ay9nAB824R2taA=;\n\th=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To:\n\t To:Cc:MIME-Version;\n b=T0O3H6bSjY73NaKnZvrSSBxM4lLmloK7sOe6CJf6pKPxGCBvs1cmXqC/CE2uMT7E6C3gj4nJXUftxj+cuhygbGpuCdO66sD5+mA4PWlQ2UsUyqcnak24Ryzm+9T1TcH3f6s3yFvRF8vAngjKeBY6m+mttYNl0YHds/XRTuY0r5I=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=FQExniY/fbSpmugBiJjHKjENNl0DOkT3zT8DJ+f5VP0=;\n b=H+AArlx+4/Q6qrxkawh7vAcqLEmCjsEl2ytG6DvNJX/keBpWyzMfLIgAoLah3c52YlnQ5bVQEYwk62JbrKbX0cxjYsSLzDHubWhbT5g10phgASUuE/eBmmhGaWiOB4BBPhcmpESNHCeUMwG7OLajFXNMP1c3PtB3rEBxduWD2W/g3Fmh2hY/4zup9MDduTYayhT8asKKPuLkDxxIGj9Z1DoV7jbUZN9nGW5vjqXg6c7Un73cxjSrtVLjKemyM/6ugJ4kNOts90xjfaYY/hXoevspnn9xZ81p3lS1nHYvbFxq7Dq85/csUrICPQDJyvkW/sVaW8PXvGDwmb1YpcFLJg==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=TNHGT6uo; arc=fail smtp.client-ip=40.93.194.22", "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com;\n dkim=pass header.d=nvidia.com; arc=none" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=FQExniY/fbSpmugBiJjHKjENNl0DOkT3zT8DJ+f5VP0=;\n b=TNHGT6uoE1svCd99/vOVahYCpLsSXpqzrKT8L4CLptMahpQpUtzasGUmv6bb/8/CkFNXsJmAY+CtRc/SbQ6wJZUE1EbOY5r7pyktYCMz7UOdhmppkoNuFQ3vziB/Z0Off71CycwxYDX7kPZL3lTByQRoj8h8QjoNKd0tDWjr2/6E4ZUFG3snHf63B6JyKJg6ckguzX6VJqFioIEtaI57pva82rn0zmC+XBDs4GOVZiedKCmQ1ipRvQdRTReALlOHoxSDV4FoTy8iANcQWbHleT9RvTC1te4jTUEXCoy4a+Eu27nOKtY0Y6bvOgIsPiPvntRWtaJtsoormiO2ibjC4A==", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "Date": "Wed, 25 Mar 2026 19:17:00 +0900", "Subject": "[PATCH v2 2/7] pwm: tegra: Avoid hard-coded max clock frequency", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260325-t264-pwm-v2-2-998d885984b3@nvidia.com>", "References": "<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>", "In-Reply-To": "<20260325-t264-pwm-v2-0-998d885984b3@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>, =?utf-8?q?Uwe_Kleine-K=C3=B6n?=\n\t=?utf-8?q?ig?= <ukleinek@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>", "Cc": "linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n Yi-Wei Wang <yiweiw@nvidia.com>, Mikko Perttunen <mperttunen@nvidia.com>", "X-Mailer": "b4 0.14.3", "X-ClientProxiedBy": "TP0P295CA0049.TWNP295.PROD.OUTLOOK.COM\n (2603:1096:910:3::20) To SJ2PR12MB9161.namprd12.prod.outlook.com\n (2603:10b6:a03:566::20)", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ2PR12MB9161:EE_|DS5PPFA3734E4BA:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5bee6ed6-3ea5-4cd6-b234-08de8a57c2b9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|366016|1800799024|10070799003|376014|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tEs6/3noNAyOugZXd6wlUWgxV6moNwX65LqdLpkFUmUx0PWYvQPgHhqBODfj8InepSgZ7s7xoMS78Vs3TLaTAEvR192c9UWph56XRp4Js5pF/o2Q4sJi8mz/V9C/aUmiyRbiqjGcLt6fc2cz6ZAZHIhy4sR6/AZhm0sgbGjY3mR88uG1xr1+kKm32vPem/0Ex1m2GWu2UPfa145MNySv5EZwWrZSbL/kOwFeOeGyeXfXDxUIR0KLMcJ2lRFGcsDHiHAle1+qG98p5UhZV2hUL8McF+c/xQxGzlolWwlJgxaFf0fAmvdhRkhf7Cxz9LD8B3NNU/5Ipt0lToy1oQQNE/ZwwJEVNZ+opP2ssiOqmNyjXrgngONvuolBS8U7HVsjUZHeoJzqxqXqaXnXn25e4sLn03XJb2DtsARt4xGlb8dutTRvzvktgxtBx46+3h/aDtSMdgWhRI1au7eldlphH8xfJ1qau4jCR8aPYbsN+UckKvulnDFG/PAnHCMPcirn9N4affxXzKM6KQiZrSlQAVhusJS+8X9u0NkAgbz7pzQcxQpigz+0SfhpACpuDGLWPl5uxlatv0Rmc5HMdKY2ddbfUz/Q8mJ7hvWSIEGWVf9aVjGs1jug55uQYRbhJ3aAzZUcvcFZqf2Da1oo2wTMudj1hJ6MT9mYq35vu5NhewOL10FJcjWAAG2MJUdzfEguCWSETDWVVpLfEYubjDcsuzmiMru9Q1vjmxaQFVP/o/hI=", "X-Forefront-Antispam-Report": "\n\tCIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SJ2PR12MB9161.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(10070799003)(376014)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "2", "X-MS-Exchange-AntiSpam-MessageData-0": "=?utf-8?q?o953m/94T7J/lmuuytlyvfaqUTxD?=\n\t=?utf-8?q?0h/C9FOHG6qMMsr9deroH3J0UyBBM2445pQzhmaW59jXUhjCwc4jfarmuxn2oe3MW?=\n\t=?utf-8?q?UFkqfPY89raF9a2zXRlmf8ESGnATCIQeGaKA7t9AWWQbWRtbmZRho3cjDYI6iFFWN?=\n\t=?utf-8?q?kl/t5LN4cKYvrFI7wkrYSILp9ZQsiQNEYAEx5wm4XqV1UBsfCfFsmXUORl+sl4Xws?=\n\t=?utf-8?q?SRDgQ9g31pPwR/Ym/amIYh6DI6QHtLq34qOEStjO/oXIIAXGFeQTLcq/d/LWPRszX?=\n\t=?utf-8?q?MNOFBzp8gsPHAcAN1Jtdj/b50REXk6dm1SPdzdbBw+ub+vpPev4MgeOyoiCi3Yrh3?=\n\t=?utf-8?q?n7AXc0XlYG2ojG+s5JxYWpfc3py6sz8znKKP3IwMt4uJxESfjq63HIC6VVniZiEcW?=\n\t=?utf-8?q?SmhZ9rdKZ17TZW78H23qZFPzM9Q+k9GskjfP3Z5ABA5IIBZeUN95qooAwLM9COKBA?=\n\t=?utf-8?q?VOw0lTmWM9upJjYr+JxNdTYvGExOfYK6tBCuCFLOsCmqj/QLR6J/S+5kgmUZa6fGp?=\n\t=?utf-8?q?6JiS9ZwWtFOKz/y/wzvMJseyvkPG54hG6S82t6wSDWrdb0hLf4fyFlCA6h+1zPK45?=\n\t=?utf-8?q?P+1+6yi9MG0FmEp6izq/V1wfUo4WFxNiDJE4P5tEvITom29ivnmG03Ocsf9kLp2nl?=\n\t=?utf-8?q?TOd9Swqj5d94RMy7N4gBtPhoyMDdSYfZw3JQFXNKWw5F6KIt0NAepiG+ShNEj4Bwp?=\n\t=?utf-8?q?JnA9vPObHg7WU9hdsGJHdGx/WaTfC3Gn8lIz0hB3r8cTM2QEzT+ePnnvogsrflV0p?=\n\t=?utf-8?q?NHkwZb0ClG3jNixMCPjFK0sjtg9K/03Kow92avD8zjZIYw/qaV/weMjePw/opUp4Y?=\n\t=?utf-8?q?mj67UuLz5F+Hm5MDD5U1wc43JAgfOJhWhs6W3NKi/HopIQBJTU1mLovyDlEflC6LP?=\n\t=?utf-8?q?9fkMzNQaMreALC35YfGwEwoiRb1h7UEMA6itGsGfc5T2MxrEBlLshG2rT6qVbpm7r?=\n\t=?utf-8?q?Z8VyL36k4Ths6GZZ2OA+u0V7QJFALfU2PPAjpAETMCV32QDYiQrkBs4cKC6JbMT0z?=\n\t=?utf-8?q?T35J18CdPmFPGhmqqdnddiGZ2oAt92RsYS7F1+3ijoM2YzJJ7YsmmHdE1cd/h4ilO?=\n\t=?utf-8?q?ZYaV2zSu/TmG/Xc+KXCaAEw0ZKKt6Ls8yLMyWiYWNtY6wjL7dAAVyd5ONyySCRvMS?=\n\t=?utf-8?q?tI1RTsteqlh8HpyTz28GtD3l+4TZ6QoUi8ITeU3ocqel25BPOjHPLDXNNrTwfLCju?=\n\t=?utf-8?q?HeS/iq3SdwIDaqY+rPayZsw2qmV0Vf9xGK4Cx4es96HjQfWrgi44ydz3DheHFlAnC?=\n\t=?utf-8?q?bQijun6q4e/u4gkNfQqT4PojxVfJwV9mp4wq2iC2u72XLhunLAsyG9ZGf4JtZaRdQ?=\n\t=?utf-8?q?64plhkf8uPG21uFZdbbFIqzyngmMxLLiI5oyYVnawPwpKhe3g6uRMQr3mMzBA/+bb?=\n\t=?utf-8?q?iVBFT5gU64LsQOBVOTsUivZN7WSZhdJxBdqqgr3pYXngbS6WLY9mq8S2tNBCuAK0B?=\n\t=?utf-8?q?QnnSc7Px/KwglV+yv4H34J4xhF9g9XxLAJ6mBE1/sbNuBqaC9YcyCVdCA8SesJcRc?=\n\t=?utf-8?q?VQ+SUwkPbwJxfae6wbkBNZZFNgTu92iItbh/E/dDXlnQ893x68wf4i78tUJgY/ZuN?=\n\t=?utf-8?q?HUJSQZq8/o0/zuo9FfU8vkT+zrUPfLbKLKE/naG/vuNI5F1X1YsU1TULlte7NpS8M?=\n\t=?utf-8?q?8zVSkxtOhErcuY18PoE7URx8QE0rzdveCBZYTyOlVaPrZnSQK6xyC591Q55Q+muru?=\n\t=?utf-8?q?CBdFyCnISRsqcDEJn?=", "X-MS-Exchange-AntiSpam-MessageData-1": "k/Gjks7tnLS7Vg==", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5bee6ed6-3ea5-4cd6-b234-08de8a57c2b9", "X-MS-Exchange-CrossTenant-AuthSource": "SJ2PR12MB9161.namprd12.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 10:17:46.7784\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 0FlEs8U9lH3cS13cMxrbp6v8oFtCN10LV+yQv3Z9tkTnleKFvwXcVqmQbfbUZ/KACKS6EUYH1K8Wx88cfa9NkQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS5PPFA3734E4BA" }, "content": "From: Yi-Wei Wang <yiweiw@nvidia.com>\n\nThe clock driving the Tegra PWM IP can be sourced from different parent\nclocks. Hence, let dev_pm_opp_set_rate() set the max clock rate based\nupon the current parent clock that can be specified via device-tree.\n\nAfter this, the Tegra194 SoC data becomes redundant, so get rid of it.\n\nSigned-off-by: Yi-Wei Wang <yiweiw@nvidia.com>\nCo-developed-by: Mikko Perttunen <mperttunen@nvidia.com>\nSigned-off-by: Mikko Perttunen <mperttunen@nvidia.com>\n---\n drivers/pwm/pwm-tegra.c | 16 +++-------------\n 1 file changed, 3 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c\nindex 172063b51d44..759b98b97b6e 100644\n--- a/drivers/pwm/pwm-tegra.c\n+++ b/drivers/pwm/pwm-tegra.c\n@@ -59,9 +59,6 @@\n \n struct tegra_pwm_soc {\n \tunsigned int num_channels;\n-\n-\t/* Maximum IP frequency for given SoCs */\n-\tunsigned long max_frequency;\n };\n \n struct tegra_pwm_chip {\n@@ -303,7 +300,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)\n \t\treturn ret;\n \n \t/* Set maximum frequency of the IP */\n-\tret = dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency);\n+\tret = dev_pm_opp_set_rate(&pdev->dev, S64_MAX);\n \tif (ret < 0) {\n \t\tdev_err(&pdev->dev, \"Failed to set max frequency: %d\\n\", ret);\n \t\tgoto put_pm;\n@@ -318,7 +315,7 @@ static int tegra_pwm_probe(struct platform_device *pdev)\n \n \t/* Set minimum limit of PWM period for the IP */\n \tpc->min_period_ns =\n-\t (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;\n+\t (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1;\n \n \tpc->rst = devm_reset_control_get_exclusive(&pdev->dev, \"pwm\");\n \tif (IS_ERR(pc->rst)) {\n@@ -397,23 +394,16 @@ static int __maybe_unused tegra_pwm_runtime_resume(struct device *dev)\n \n static const struct tegra_pwm_soc tegra20_pwm_soc = {\n \t.num_channels = 4,\n-\t.max_frequency = 48000000UL,\n };\n \n static const struct tegra_pwm_soc tegra186_pwm_soc = {\n \t.num_channels = 1,\n-\t.max_frequency = 102000000UL,\n-};\n-\n-static const struct tegra_pwm_soc tegra194_pwm_soc = {\n-\t.num_channels = 1,\n-\t.max_frequency = 408000000UL,\n };\n \n static const struct of_device_id tegra_pwm_of_match[] = {\n \t{ .compatible = \"nvidia,tegra20-pwm\", .data = &tegra20_pwm_soc },\n \t{ .compatible = \"nvidia,tegra186-pwm\", .data = &tegra186_pwm_soc },\n-\t{ .compatible = \"nvidia,tegra194-pwm\", .data = &tegra194_pwm_soc },\n+\t{ .compatible = \"nvidia,tegra194-pwm\", .data = &tegra186_pwm_soc },\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);\n", "prefixes": [ "v2", "2/7" ] }