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GET /api/patches/2215742/?format=api
{ "id": 2215742, "url": "http://patchwork.ozlabs.org/api/patches/2215742/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260325-ipq5210_boot_to_shell-v3-2-9c7360d19d10@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325-ipq5210_boot_to_shell-v3-2-9c7360d19d10@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-25T09:19:10", "name": "[v3,2/2] arm64: dts: qcom: add IPQ5210 SoC and rdp504 board support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8984370410adf2d2c7a0ce1d377b30bd621ab655", "submitter": { "id": 90386, "url": "http://patchwork.ozlabs.org/api/people/90386/?format=api", "name": "Kathiravan Thirumoorthy", "email": "kathiravan.thirumoorthy@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260325-ipq5210_boot_to_shell-v3-2-9c7360d19d10@oss.qualcomm.com/mbox/", "series": [ { "id": 497399, "url": "http://patchwork.ozlabs.org/api/series/497399/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=497399", "date": "2026-03-25T09:19:08", "name": "Add minimal boot support for Qualcomm IPQ5210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497399/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215742/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215742/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34117-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=dSMWR9Jx;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=gyg4WPvq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260325-ipq5210_boot_to_shell-v3-2-9c7360d19d10@oss.qualcomm.com>", "References": "\n <20260325-ipq5210_boot_to_shell-v3-0-9c7360d19d10@oss.qualcomm.com>", "In-Reply-To": "\n <20260325-ipq5210_boot_to_shell-v3-0-9c7360d19d10@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>,\n Michael Turquette <mturquette@baylibre.com>,\n Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Philipp Zabel <p.zabel@pengutronix.de>,\n Konrad Dybcio <konradybcio@kernel.org>,\n Robert Marko <robimarko@gmail.com>,\n Guru Das Srinagesh <linux@gurudas.dev>,\n Linus Walleij <linusw@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-gpio@vger.kernel.org,\n Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>", "X-Mailer": "b4 0.15.0", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774430351; l=10087;\n i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906;\n h=from:subject:message-id; bh=bY0kdgk93iJpCBbfL/J18AveBPoh0X+n44UUVxZE/RI=;\n b=JWjjCZHoUq17XXE7juuXq0ym17yhxS+WbFa9lxkfp3i9dOE3f7bcpYDz2RlKXJWevZ7uHwuC9\n yx6i+wfBCWGDm7FcB0ZteY1MfWxp4kiBcVsr/VBMae8exOq8MVQNCgo", "X-Developer-Key": "i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519;\n pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM=", "X-Proofpoint-ORIG-GUID": "Z78PK63k3dbdDV_KEqS2fPpI0OunHlLN", "X-Proofpoint-GUID": "Z78PK63k3dbdDV_KEqS2fPpI0OunHlLN", "X-Authority-Analysis": "v=2.4 cv=Q73fIo2a c=1 sm=1 tr=0 ts=69c3a8a2 cx=c_pps\n a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22\n a=EUspDBNiAAAA:8 a=Nb4-WWA3gxlMGfkpIFUA:9 a=QEXdDO2ut3YA:10\n a=zc0IvFSfCIW2DFIPzwfm:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzI1MDA2NCBTYWx0ZWRfX8BaWSuw+7+MM\n isax3D19F9XCEejN1gZhx22AXWL8sU20C4LR94adLfdfQeSi7LThb95j0/6ELY2lPTLNc4uh90h\n tqxABLafK0m9bxxWOynIzHX26NCaeJr4Ms1Q6o9GrGyHeZVDqCm/eeQH6GgBk48ZQxdJo6VRKg+\n G+Ftpoxx0LbnxujFcAEvTPNNPw3oRByDbz3FRomcn5BSqebo6eHm+hNLbw4FOKwkAhAKJ8vURnS\n lkTp4xDJ2Hz4Txca59hsVSi75DQwLgyYM4LKmMP8bJ8eJl9EeL0A2u8rW05W+CPb3wBbIrRn3AD\n Z4H8VirxTvCOt7UTOWgesTxu3OcqN1UpmBAzEJ8jXMZLkRqLW2Kuu8UrJhNmt3lsYpd68dy02iH\n ts75MgkR3/Hh+IyUlyHaPKQzKeqnW3fzmQZCpb9z1W2zsmcyCT0/6T5BhLijiQsXElecTyl06m4\n UMo5APuwgsKILJgpe6Q==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-25_03,2026-03-24_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0\n malwarescore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603250064" }, "content": "Add initial device tree support for the Qualcomm IPQ5210 SoC and\nrdp504 board.\n\nSigned-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>\n---\n arch/arm64/boot/dts/qcom/Makefile | 1 +\n arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 79 +++++++\n arch/arm64/boot/dts/qcom/ipq5210.dtsi | 311 ++++++++++++++++++++++++++++\n 3 files changed, 391 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile\nindex d69e5f3132c4..c46d94bb6dd5 100644\n--- a/arch/arm64/boot/dts/qcom/Makefile\n+++ b/arch/arm64/boot/dts/qcom/Makefile\n@@ -23,6 +23,7 @@ hamoa-iot-evk-el2-dtbs\t:= hamoa-iot-evk.dtb x1-el2.dtbo\n dtb-$(CONFIG_ARCH_QCOM)\t+= hamoa-iot-evk-el2.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5018-rdp432-c2.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5018-tplink-archer-ax55-v1.dtb\n+dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5210-rdp504.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5332-rdp441.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5332-rdp442.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5332-rdp468.dtb\ndiff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts\nnew file mode 100644\nindex 000000000000..941f866ecfe9\n--- /dev/null\n+++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts\n@@ -0,0 +1,79 @@\n+// SPDX-License-Identifier: BSD-3-Clause\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+/dts-v1/;\n+\n+#include \"ipq5210.dtsi\"\n+\n+/ {\n+\tmodel = \"Qualcomm Technologies, Inc. IPQ5210 RDP504\";\n+\tcompatible = \"qcom,ipq5210-rdp504\", \"qcom,ipq5210\";\n+\n+\taliases {\n+\t\tserial0 = &uart1;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0\";\n+\t};\n+};\n+\n+&sdhc {\n+\tmax-frequency = <192000000>;\n+\tbus-width = <4>;\n+\tmmc-ddr-1_8v;\n+\tmmc-hs200-1_8v;\n+\tpinctrl-0 = <&sdhc_default_state>;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+&sleep_clk {\n+\tclock-frequency = <32000>;\n+};\n+\n+&tlmm {\n+\tqup_uart1_default_state: qup-uart1-default-state {\n+\t\tpins = \"gpio38\", \"gpio39\";\n+\t\tfunction = \"qup_se1\";\n+\t\tdrive-strength = <6>;\n+\t\tbias-pull-down;\n+\t};\n+\n+\tsdhc_default_state: sdhc-default-state {\n+\t\tclk-pins {\n+\t\t\tpins = \"gpio5\";\n+\t\t\tfunction = \"sdc_clk\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tcmd-pins {\n+\t\t\tpins = \"gpio4\";\n+\t\t\tfunction = \"sdc_cmd\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tdata-pins {\n+\t\t\tpins = \"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\";\n+\t\t\tfunction = \"sdc_data\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+};\n+\n+&uart1 {\n+\tpinctrl-0 = <&qup_uart1_default_state>;\n+\tpinctrl-names = \"default\";\n+\n+\tstatus = \"okay\";\n+};\n+\n+&xo_board {\n+\tclock-frequency = <24000000>;\n+};\ndiff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi\nnew file mode 100644\nindex 000000000000..3761eb03ab24\n--- /dev/null\n+++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi\n@@ -0,0 +1,311 @@\n+// SPDX-License-Identifier: BSD-3-Clause\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/clock/qcom,ipq5210-gcc.h>\n+#include <dt-bindings/reset/qcom,ipq5210-gcc.h>\n+\n+/ {\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\tinterrupt-parent = <&intc>;\n+\n+\tclocks {\n+\t\tsleep_clk: sleep-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\n+\t\txo_board: xo-board-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x0>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t};\n+\n+\t\tcpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x1>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t};\n+\n+\t\tcpu@2 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x2>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t};\n+\n+\t\tcpu@3 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x3>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t};\n+\n+\t\tl2_0: l2-cache {\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-level = <2>;\n+\t\t\tcache-unified;\n+\t\t};\n+\t};\n+\n+\tfirmware {\n+\t\toptee {\n+\t\t\tcompatible = \"linaro,optee-tz\";\n+\t\t\tmethod = \"smc\";\n+\t\t};\n+\n+\t\tscm {\n+\t\t\tcompatible = \"qcom,scm-ipq5210\", \"qcom,scm\";\n+\t\t};\n+\t};\n+\n+\tmemory@80000000 {\n+\t\tdevice_type = \"memory\";\n+\t\t/* We expect the bootloader to fill in the size */\n+\t\treg = <0x0 0x80000000 0x0 0x0>;\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,cortex-a53-pmu\";\n+\t\tinterrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t};\n+\n+\tpsci {\n+\t\tcompatible = \"arm,psci-1.0\";\n+\t\tmethod = \"smc\";\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\tbootloader@87800000 {\n+\t\t\treg = <0x0 0x87800000 0x0 0x400000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\tsmem@87c00000 {\n+\t\t\tcompatible = \"qcom,smem\";\n+\t\t\treg = <0x0 0x87c00000 0x0 0x40000>;\n+\t\t\tno-map;\n+\n+\t\t\thwlocks = <&tcsr_mutex 3>;\n+\t\t};\n+\n+\t\ttfa@87d00000 {\n+\t\t\treg = <0x0 0x87d00000 0x0 0x80000>;\n+\t\t\tno-map;\n+\t\t};\n+\n+\t\toptee@87d80000 {\n+\t\t\treg = <0x0 0x87d80000 0x0 0x280000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+\n+\tsoc@0 {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tdma-ranges = <0 0 0 0 0x10 0>;\n+\t\tranges = <0 0 0 0 0x10 0>;\n+\n+\t\ttlmm: pinctrl@1000000 {\n+\t\t\tcompatible = \"qcom,ipq5210-tlmm\";\n+\t\t\treg = <0x0 0x01000000 0x0 0x300000>;\n+\t\t\tinterrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&tlmm 0 0 54>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tgcc: clock-controller@1800000 {\n+\t\t\tcompatible = \"qcom,ipq5210-gcc\";\n+\t\t\treg = <0x0 0x01800000 0x0 0x40000>;\n+\t\t\tclocks = <&xo_board>,\n+\t\t\t\t <&sleep_clk>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t};\n+\n+\t\ttcsr_mutex: hwlock@1905000 {\n+\t\t\tcompatible = \"qcom,tcsr-mutex\";\n+\t\t\treg = <0x0 0x01905000 0x0 0x20000>;\n+\t\t\t#hwlock-cells = <1>;\n+\t\t};\n+\n+\t\tqupv3: geniqup@1ac0000 {\n+\t\t\tcompatible = \"qcom,geni-se-qup\";\n+\t\t\treg = <0x0 0x01ac0000 0x0 0x2000>;\n+\t\t\tclocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,\n+\t\t\t\t <&gcc GCC_QUPV3_AHB_SLV_CLK>;\n+\t\t\tclock-names = \"m-ahb\", \"s-ahb\";\n+\t\t\tranges;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\n+\t\t\tuart1: serial@1a84000 {\n+\t\t\t\tcompatible = \"qcom,geni-debug-uart\";\n+\t\t\t\treg = <0x0 0x01a84000 0x0 0x4000>;\n+\t\t\t\tclocks = <&gcc GCC_QUPV3_WRAP_SE1_CLK>;\n+\t\t\t\tclock-names = \"se\";\n+\t\t\t\tinterrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tsdhc: mmc@7804000 {\n+\t\t\tcompatible = \"qcom,ipq5210-sdhci\", \"qcom,sdhci-msm-v5\";\n+\t\t\treg = <0x0 0x07804000 0x0 0x1000>,\n+\t\t\t <0x0 0x07805000 0x0 0x1000>;\n+\t\t\treg-names = \"hc\",\n+\t\t\t\t \"cqhci\";\n+\n+\t\t\tinterrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"hc_irq\",\n+\t\t\t\t\t \"pwr_irq\";\n+\n+\t\t\tclocks = <&gcc GCC_SDCC1_AHB_CLK>,\n+\t\t\t\t <&gcc GCC_SDCC1_APPS_CLK>,\n+\t\t\t\t <&xo_board>;\n+\t\t\tclock-names = \"iface\",\n+\t\t\t\t \"core\",\n+\t\t\t\t \"xo\";\n+\t\t\tnon-removable;\n+\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tintc: interrupt-controller@b000000 {\n+\t\t\tcompatible = \"qcom,msm-qgic2\";\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\treg = <0x0 0xb000000 0x0 0x1000>,\n+\t\t\t <0x0 0xb002000 0x0 0x1000>,\n+\t\t\t <0x0 0xb001000 0x0 0x1000>,\n+\t\t\t <0x0 0xb004000 0x0 0x1000>;\n+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges = <0 0 0 0x0b00c000 0 0x3000>;\n+\n+\t\t\tv2m0: v2m@0 {\n+\t\t\t\tcompatible = \"arm,gic-v2m-frame\";\n+\t\t\t\treg = <0x0 0x0 0x0 0xffd>;\n+\t\t\t\tmsi-controller;\n+\t\t\t};\n+\n+\t\t\tv2m1: v2m@1000 {\n+\t\t\t\tcompatible = \"arm,gic-v2m-frame\";\n+\t\t\t\treg = <0x0 0x00001000 0x0 0xffd>;\n+\t\t\t\tmsi-controller;\n+\t\t\t};\n+\n+\t\t\tv2m2: v2m@2000 {\n+\t\t\t\tcompatible = \"arm,gic-v2m-frame\";\n+\t\t\t\treg = <0x0 0x00002000 0x0 0xffd>;\n+\t\t\t\tmsi-controller;\n+\t\t\t};\n+\t\t};\n+\n+\t\ttimer@b120000 {\n+\t\t\tcompatible = \"arm,armv7-timer-mem\";\n+\t\t\treg = <0x0 0x0b120000 0x0 0x1000>;\n+\t\t\tranges = <0 0 0 0x10000000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tframe@b121000 {\n+\t\t\t\tframe-number = <0>;\n+\t\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\treg = <0x0b121000 0x1000>,\n+\t\t\t\t <0x0b122000 0x1000>;\n+\t\t\t};\n+\n+\t\t\tframe@b123000 {\n+\t\t\t\tframe-number = <1>;\n+\t\t\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\treg = <0x0b123000 0x1000>;\n+\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b124000 {\n+\t\t\t\tframe-number = <2>;\n+\t\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\treg = <0x0b124000 0x1000>;\n+\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b125000 {\n+\t\t\t\tframe-number = <3>;\n+\t\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\treg = <0x0b125000 0x1000>;\n+\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b126000 {\n+\t\t\t\tframe-number = <4>;\n+\t\t\t\tinterrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\treg = <0x0b126000 0x1000>;\n+\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b127000 {\n+\t\t\t\tframe-number = <5>;\n+\t\t\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\treg = <0x0b127000 0x1000>;\n+\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b128000 {\n+\t\t\t\tframe-number = <6>;\n+\t\t\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\treg = <0x0b128000 0x1000>;\n+\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n+\t};\n+};\n", "prefixes": [ "v3", "2/2" ] }