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GET /api/patches/2215666/?format=api
{ "id": 2215666, "url": "http://patchwork.ozlabs.org/api/patches/2215666/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1774403912-210670-4-git-send-email-shawn.lin@rock-chips.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1774403912-210670-4-git-send-email-shawn.lin@rock-chips.com>", "list_archive_url": null, "date": "2026-03-25T01:58:32", "name": "[v5,3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition trace support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c6b62deebaf9afac012f30cf4d84d0a74ca44f86", "submitter": { "id": 66993, "url": "http://patchwork.ozlabs.org/api/people/66993/?format=api", "name": "Shawn Lin", "email": "shawn.lin@rock-chips.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1774403912-210670-4-git-send-email-shawn.lin@rock-chips.com/mbox/", "series": [ { "id": 497375, "url": "http://patchwork.ozlabs.org/api/series/497375/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497375", "date": "2026-03-25T01:58:29", "name": "PCI Controller event and LTSSM tracepoint support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/497375/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215666/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215666/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51006-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=gz89Ybf3;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-51006-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=\"gz89Ybf3\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=220.197.32.69", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=rock-chips.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org [104.64.211.4])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgWFg1250z1xy3\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 13:34:31 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id E45A93010778\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 02:34:28 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 8D4EC282F2F;\n\tWed, 25 Mar 2026 02:34:27 +0000 (UTC)", "from mail-m3269.qiye.163.com (mail-m3269.qiye.163.com\n [220.197.32.69])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id A0A491531E8;\n\tWed, 25 Mar 2026 02:34:23 +0000 (UTC)", "from localhost.localdomain (unknown [58.22.7.114])\n\tby smtp.qiye.163.com (Hmail) with ESMTP id 382e78d8b;\n\tWed, 25 Mar 2026 09:58:46 +0800 (GMT+08:00)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774406067; cv=none;\n b=irL53jsoYlhQAQRhppOph2I8iYv3ka3MkOUK/BY44Sy8bL01gH8iIyWrtbfZeCwIMilIqsnHE/BK55N6Gap6Ut4YP1Rb5UhetDLnfwAeWxLOzutbC5B5vHAPi1V/J9l+0G2Yzdjjextmq1+A5YShlr0Q1507Jt0gWliMPsmXDFo=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774406067; c=relaxed/simple;\n\tbh=xEPSg9x35pAm5jF0bqxjz5w5egKkzWVsk078GyOjTy4=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References;\n b=ZYkOUAGSppNyDna+er0wqyhhp3zGvUt/L5LHxI9duRDJFWEONYaMTQok8njSzz7ClKGBKCKe2P2FJvWvpgjQ4D21BVb+R13xwvEvss6tChqwMB0cFDB4Ej4gIajSsqt55jsDAxzKd80aGs5rukD1HjEwUbAcsSwCLZQC/eVD154=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com;\n spf=pass smtp.mailfrom=rock-chips.com;\n dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=gz89Ybf3; arc=none smtp.client-ip=220.197.32.69", "From": "Shawn Lin <shawn.lin@rock-chips.com>", "To": "Manivannan Sadhasivam <mani@kernel.org>,\n\tBjorn Helgaas <bhelgaas@google.com>", "Cc": "linux-rockchip@lists.infradead.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-trace-kernel@vger.kernel.org,\n\tlinux-doc@vger.kernel.org,\n\tSteven Rostedt <rostedt@goodmis.org>,\n\tShawn Lin <shawn.lin@rock-chips.com>", "Subject": "[PATCH v5 3/3] PCI: dw-rockchip: Add pcie_ltssm_state_transition\n trace support", "Date": "Wed, 25 Mar 2026 09:58:32 +0800", "Message-Id": "<1774403912-210670-4-git-send-email-shawn.lin@rock-chips.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>", "References": "<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>", "X-HM-Tid": "0a9d22b73a1309cckunm61c156f0a558ae", "X-HM-MType": "1", "X-HM-Spam-Status": "e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQkMdTFYaGR9JSUtITxpOSR5WFRQJFh\n\toXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0\n\thVSktLVUpCS0tZBg++", "DKIM-Signature": "a=rsa-sha256;\n\tb=gz89Ybf3vXAzPkxRsV/sY2TRC/F1Qbuf1E1T8HZlGmzRAn3aNHv0Xl+P7Z7PriyaDTV+BS23CZIxnqYqxJAhaPatqmTSOJZEuujBevwYJRn8Qq8TSyw5eW7DL1s3DizcfhMPu7SH5zvTCs6JZVxSGXrOQ8CtX5ZCqRycMJp4zao=;\n s=default; c=relaxed/relaxed; d=rock-chips.com; v=1;\n\tbh=mVQ3wBTObZTHeiuagy3/HA6ngtLOnHt9udd3dqVawG4=;\n\th=date:mime-version:subject:message-id:from;", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>" }, "content": "Rockchip platforms provide a 64x4 bytes debug FIFO to trace the\nLTSSM history. Any LTSSM change will be recorded. It's useful\nfor debug purpose, for example link failure, etc.\n\nSigned-off-by: Shawn Lin <shawn.lin@rock-chips.com>\n---\n\nChanges in v5:\n- rebase\n- use trace_pcie_ltssm_state_transition_enabled()\n\nChanges in v4:\n- skip trace if pci_ltssm_tp_enabled() is false.(Steven)\n- wrap into 80 columns(Bjorn)\n\nChanges in v3:\n- reorder variables(Mani)\n- rename loop to i; rename en to enable(Mani)\n- use FIELD_GET(Mani)\n- add comment about how the FIFO works(Mani)\n\nChanges in v2:\n- use tracepoint\n\n drivers/pci/controller/dwc/pcie-dw-rockchip.c | 111 ++++++++++++++++++++++++++\n 1 file changed, 111 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c\nindex bb5d1a3..e737103 100644\n--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c\n+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c\n@@ -22,6 +22,8 @@\n #include <linux/platform_device.h>\n #include <linux/regmap.h>\n #include <linux/reset.h>\n+#include <linux/workqueue.h>\n+#include <trace/events/pci_controller.h>\n \n #include \"../../pci.h\"\n #include \"pcie-designware.h\"\n@@ -73,6 +75,20 @@\n #define PCIE_CLIENT_CDM_RASDES_TBA_L1_1\tBIT(4)\n #define PCIE_CLIENT_CDM_RASDES_TBA_L1_2\tBIT(5)\n \n+/* Debug FIFO information */\n+#define PCIE_CLIENT_DBG_FIFO_MODE_CON\t0x310\n+#define PCIE_CLIENT_DBG_EN\t\t0xffff0007\n+#define PCIE_CLIENT_DBG_DIS\t\t0xffff0000\n+#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0\t0x320\n+#define PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1\t0x324\n+#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0\t0x328\n+#define PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1\t0x32c\n+#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000\n+#define PCIE_CLIENT_DBG_FIFO_STATUS\t0x350\n+#define PCIE_DBG_FIFO_RATE_MASK\tGENMASK(22, 20)\n+#define PCIE_DBG_FIFO_L1SUB_MASK\tGENMASK(10, 8)\n+#define PCIE_DBG_LTSSM_HISTORY_CNT\t64\n+\n /* Hot Reset Control Register */\n #define PCIE_CLIENT_HOT_RESET_CTRL\t0x180\n #define PCIE_LTSSM_APP_DLY2_EN\t\tBIT(1)\n@@ -98,6 +114,7 @@ struct rockchip_pcie {\n \tstruct irq_domain *irq_domain;\n \tconst struct rockchip_pcie_of_data *data;\n \tbool supports_clkreq;\n+\tstruct delayed_work trace_work;\n };\n \n struct rockchip_pcie_of_data {\n@@ -208,6 +225,96 @@ static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)\n \treturn rockchip_pcie_get_ltssm_reg(rockchip) & PCIE_LTSSM_STATUS_MASK;\n }\n \n+#ifdef CONFIG_TRACING\n+static void rockchip_pcie_ltssm_trace_work(struct work_struct *work)\n+{\n+\tstruct rockchip_pcie *rockchip = container_of(work,\n+\t\t\t\t\t\tstruct rockchip_pcie,\n+\t\t\t\t\t\ttrace_work.work);\n+\tstruct dw_pcie *pci = &rockchip->pci;\n+\tenum dw_pcie_ltssm state;\n+\tu32 i, l1ss, prev_val = DW_PCIE_LTSSM_UNKNOWN, rate, val;\n+\n+\tif (!trace_pcie_ltssm_state_transition_enabled())\n+\t\tgoto skip_trace;\n+\n+\tfor (i = 0; i < PCIE_DBG_LTSSM_HISTORY_CNT; i++) {\n+\t\tval = rockchip_pcie_readl_apb(rockchip,\n+\t\t\t\tPCIE_CLIENT_DBG_FIFO_STATUS);\n+\t\trate = FIELD_GET(PCIE_DBG_FIFO_RATE_MASK, val);\n+\t\tl1ss = FIELD_GET(PCIE_DBG_FIFO_L1SUB_MASK, val);\n+\t\tval = FIELD_GET(PCIE_LTSSM_STATUS_MASK, val);\n+\n+\t\t/*\n+\t\t * Hardware Mechanism: The ring FIFO employs two tracking\n+\t\t * counters:\n+\t\t * - 'last-read-point': maintains the user's last read position\n+\t\t * - 'last-valid-point': tracks the HW's last state update\n+\t\t *\n+\t\t * Software Handling: When two consecutive LTSSM states are\n+\t\t * identical, it indicates invalid subsequent data in the FIFO.\n+\t\t * In this case, we skip the remaining entries. The dual counter\n+\t\t * design ensures that on the next state transition, reading can\n+\t\t * resume from the last user position.\n+\t\t */\n+\t\tif ((i > 0 && val == prev_val) || val > DW_PCIE_LTSSM_RCVRY_EQ3)\n+\t\t\tbreak;\n+\n+\t\tstate = prev_val = val;\n+\t\tif (val == DW_PCIE_LTSSM_L1_IDLE) {\n+\t\t\tif (l1ss == 2)\n+\t\t\t\tstate = DW_PCIE_LTSSM_L1_2;\n+\t\t\telse if (l1ss == 1)\n+\t\t\t\tstate = DW_PCIE_LTSSM_L1_1;\n+\t\t}\n+\n+\t\ttrace_pcie_ltssm_state_transition(dev_name(pci->dev),\n+\t\t\t\tdw_pcie_ltssm_status_string(state),\n+\t\t\t\t((rate + 1) > pci->max_link_speed) ?\n+\t\t\t\tPCI_SPEED_UNKNOWN : PCIE_SPEED_2_5GT + rate);\n+\t}\n+\n+skip_trace:\n+\tschedule_delayed_work(&rockchip->trace_work, msecs_to_jiffies(5000));\n+}\n+\n+static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,\n+\t\t\t\t bool enable)\n+{\n+\tif (enable) {\n+\t\trockchip_pcie_writel_apb(rockchip,\n+\t\t\t\t\t PCIE_CLIENT_DBG_TRANSITION_DATA,\n+\t\t\t\t\t PCIE_CLIENT_DBG_FIFO_PTN_HIT_D0);\n+\t\trockchip_pcie_writel_apb(rockchip,\n+\t\t\t\t\t PCIE_CLIENT_DBG_TRANSITION_DATA,\n+\t\t\t\t\t PCIE_CLIENT_DBG_FIFO_PTN_HIT_D1);\n+\t\trockchip_pcie_writel_apb(rockchip,\n+\t\t\t\t\t PCIE_CLIENT_DBG_TRANSITION_DATA,\n+\t\t\t\t\t PCIE_CLIENT_DBG_FIFO_TRN_HIT_D0);\n+\t\trockchip_pcie_writel_apb(rockchip,\n+\t\t\t\t\t PCIE_CLIENT_DBG_TRANSITION_DATA,\n+\t\t\t\t\t PCIE_CLIENT_DBG_FIFO_TRN_HIT_D1);\n+\t\trockchip_pcie_writel_apb(rockchip,\n+\t\t\t\t\t PCIE_CLIENT_DBG_EN,\n+\t\t\t\t\t PCIE_CLIENT_DBG_FIFO_MODE_CON);\n+\n+\t\tINIT_DELAYED_WORK(&rockchip->trace_work,\n+\t\t\t\t rockchip_pcie_ltssm_trace_work);\n+\t\tschedule_delayed_work(&rockchip->trace_work, 0);\n+\t} else {\n+\t\trockchip_pcie_writel_apb(rockchip,\n+\t\t\t\t\t PCIE_CLIENT_DBG_DIS,\n+\t\t\t\t\t PCIE_CLIENT_DBG_FIFO_MODE_CON);\n+\t\tcancel_delayed_work_sync(&rockchip->trace_work);\n+\t}\n+}\n+#else\n+static void rockchip_pcie_ltssm_trace(struct rockchip_pcie *rockchip,\n+\t\t\t\t bool enable)\n+{\n+}\n+#endif\n+\n static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)\n {\n \trockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,\n@@ -291,6 +398,9 @@ static int rockchip_pcie_start_link(struct dw_pcie *pci)\n \t * 100us as we don't know how long should the device need to reset.\n \t */\n \tmsleep(PCIE_T_PVPERL_MS);\n+\n+\trockchip_pcie_ltssm_trace(rockchip, true);\n+\n \tgpiod_set_value_cansleep(rockchip->rst_gpio, 1);\n \n \treturn 0;\n@@ -301,6 +411,7 @@ static void rockchip_pcie_stop_link(struct dw_pcie *pci)\n \tstruct rockchip_pcie *rockchip = to_rockchip_pcie(pci);\n \n \trockchip_pcie_disable_ltssm(rockchip);\n+\trockchip_pcie_ltssm_trace(rockchip, false);\n }\n \n static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)\n", "prefixes": [ "v5", "3/3" ] }