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GET /api/patches/2215663/?format=api
{ "id": 2215663, "url": "http://patchwork.ozlabs.org/api/patches/2215663/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1774403912-210670-2-git-send-email-shawn.lin@rock-chips.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1774403912-210670-2-git-send-email-shawn.lin@rock-chips.com>", "list_archive_url": null, "date": "2026-03-25T01:58:30", "name": "[v5,1/3] PCI: trace: Add PCI controller LTSSM transition tracepoint", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4ff198f8fc459676b6e030a551fe98faeb53705e", "submitter": { "id": 66993, "url": "http://patchwork.ozlabs.org/api/people/66993/?format=api", "name": "Shawn Lin", "email": "shawn.lin@rock-chips.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1774403912-210670-2-git-send-email-shawn.lin@rock-chips.com/mbox/", "series": [ { "id": 497375, "url": "http://patchwork.ozlabs.org/api/series/497375/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497375", "date": "2026-03-25T01:58:29", "name": "PCI Controller event and LTSSM tracepoint support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/497375/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215663/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215663/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51003-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=rock-chips.com header.i=@rock-chips.com\n header.a=rsa-sha256 header.s=default header.b=h7RxCBke;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-51003-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=\"h7RxCBke\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=45.254.49.248", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=rock-chips.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgVcg178cz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 13:05:55 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 3E8CB300F138\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 01:58:55 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 0A51A27A91D;\n\tWed, 25 Mar 2026 01:58:54 +0000 (UTC)", "from mail-m49248.qiye.163.com (mail-m49248.qiye.163.com\n [45.254.49.248])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id E39BF279DC3;\n\tWed, 25 Mar 2026 01:58:50 +0000 (UTC)", "from localhost.localdomain (unknown [58.22.7.114])\n\tby smtp.qiye.163.com (Hmail) with ESMTP id 382e59d5b;\n\tWed, 25 Mar 2026 09:58:41 +0800 (GMT+08:00)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774403933; cv=none;\n b=WZh/oP8QXYbumUeXpbrds+oI9CCKYLxt5yEOxsOTUk1Mh5KjTM++xUAa+rn5w+zFJK2BIBXtZS1jX/9N+78zUpioL6gXQzE4g2Eqe0+1O1d5RY+UL2oPVR9+I6v5x3UnqVdX8mVgsmPD/aDa5gD5eAXkUW+GD+o2tnSC2ec2NZA=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774403933; c=relaxed/simple;\n\tbh=QalUjP7AkMbAsghFE2vnYPKXnA1KvR2kiGM3lY0+zu4=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References;\n b=iIbRohg/71JnCoNRJnjPdiMK++4NCoMp9kQxhUsGukDiCZqhw2PJve3x8pfBJzpYpB3+JOc7nfTxXqtkFePb984qFiehkec/98wM+6ToTvGsbIFoK/cr3m6cU/KAjv6/EnXahNa6Rkmd+/PHIXz6X/WnWSiz4cdIBDLDFiOe6jk=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=rock-chips.com;\n spf=pass smtp.mailfrom=rock-chips.com;\n dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com\n header.b=h7RxCBke; arc=none smtp.client-ip=45.254.49.248", "From": "Shawn Lin <shawn.lin@rock-chips.com>", "To": "Manivannan Sadhasivam <mani@kernel.org>,\n\tBjorn Helgaas <bhelgaas@google.com>", "Cc": "linux-rockchip@lists.infradead.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-trace-kernel@vger.kernel.org,\n\tlinux-doc@vger.kernel.org,\n\tSteven Rostedt <rostedt@goodmis.org>,\n\tShawn Lin <shawn.lin@rock-chips.com>", "Subject": "[PATCH v5 1/3] PCI: trace: Add PCI controller LTSSM transition\n tracepoint", "Date": "Wed, 25 Mar 2026 09:58:30 +0800", "Message-Id": "<1774403912-210670-2-git-send-email-shawn.lin@rock-chips.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>", "References": "<1774403912-210670-1-git-send-email-shawn.lin@rock-chips.com>", "X-HM-Tid": "0a9d22b7256909cckunm61c156f0a5586c", "X-HM-MType": "1", "X-HM-Spam-Status": "e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly\n\ttZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQh4eS1ZOTEtLSkNDTR5OSEpWFRQJFh\n\toXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpOTE\n\tpVSktLVUpCS0tZBg++", "DKIM-Signature": "a=rsa-sha256;\n\tb=h7RxCBkeNdV3RdS1lL07SH+zn9re32xt2UAL9i4tKl7hfxKg5oUcvxmx8t2UQDmVajPAA+NirUI6MCkqOkCa3nC+Rk4Ps9m8F9/uHdW3sO0o7/xCuBgBaC1yJDNXptRVndtg2ZWutSEVeppWEiAlUg5IVsmzxoPU8UcAgNIxRSc=;\n s=default; c=relaxed/relaxed; d=rock-chips.com; v=1;\n\tbh=QSGJAYrwVyaJSE6SdOF9MFVaSP3OU7Hp4gce1A1jKiI=;\n\th=date:mime-version:subject:message-id:from;", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>" }, "content": "Some platforms may provide LTSSM trace functionality, recording historical\nLTSSM state transition information. This is very useful for debugging, such\nas when certain devices cannot be recognized or link broken during test.\nImplement the pci controller tracepoint for recording LTSSM and rate.\n\nSigned-off-by: Shawn Lin <shawn.lin@rock-chips.com>\n---\n\nChanges in v5:\n- use EM/EMe instead\n- remove reg/unreg function and back to use TRACE_EVENT\n\nChanges in v4:\n- use TRACE_EVENT_FN to notify when to start and stop the tracepoint,\n and export pci_ltssm_tp_enabled() for host drivers to use\n\nChanges in v3:\n- add TRACE_DEFINE_ENUM for all enums(Steven Rostedt)\n\nChanges in v2: None\n\n drivers/pci/trace.c | 1 +\n include/trace/events/pci_controller.h | 58 +++++++++++++++++++++++++++++++++++\n 2 files changed, 59 insertions(+)\n create mode 100644 include/trace/events/pci_controller.h", "diff": "diff --git a/drivers/pci/trace.c b/drivers/pci/trace.c\nindex cf11abc..c1da9d3 100644\n--- a/drivers/pci/trace.c\n+++ b/drivers/pci/trace.c\n@@ -9,3 +9,4 @@\n \n #define CREATE_TRACE_POINTS\n #include <trace/events/pci.h>\n+#include <trace/events/pci_controller.h>\ndiff --git a/include/trace/events/pci_controller.h b/include/trace/events/pci_controller.h\nnew file mode 100644\nindex 0000000..a4b387c\n--- /dev/null\n+++ b/include/trace/events/pci_controller.h\n@@ -0,0 +1,58 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+#undef TRACE_SYSTEM\n+#define TRACE_SYSTEM pci_controller\n+\n+#if !defined(_TRACE_HW_EVENT_PCI_CONTROLLER_H) || defined(TRACE_HEADER_MULTI_READ)\n+#define _TRACE_HW_EVENT_PCI_CONTROLLER_H\n+\n+#include <uapi/linux/pci_regs.h>\n+#include <linux/tracepoint.h>\n+\n+#define RATE\t\t\t\t\t\\\n+\tEM(PCIE_SPEED_2_5GT, \"2.5 GT/s\")\t\\\n+\tEM(PCIE_SPEED_5_0GT, \"5.0 GT/s\")\t\\\n+\tEM(PCIE_SPEED_8_0GT, \"8.0 GT/s\")\t\\\n+\tEM(PCIE_SPEED_16_0GT, \"16.0 GT/s\")\t\\\n+\tEM(PCIE_SPEED_32_0GT, \"32.0 GT/s\")\t\\\n+\tEM(PCIE_SPEED_64_0GT, \"64.0 GT/s\")\t\\\n+\tEMe(PCI_SPEED_UNKNOWN, \"Unknown\")\n+\n+\n+#undef EM\n+#undef EMe\n+#define EM(a, b)\tTRACE_DEFINE_ENUM(a);\n+#define EMe(a, b)\tTRACE_DEFINE_ENUM(a);\n+\n+RATE\n+\n+#undef EM\n+#undef EMe\n+#define EM(a, b)\t{a, b},\n+#define EMe(a, b)\t{a, b}\n+\n+TRACE_EVENT(pcie_ltssm_state_transition,\n+\tTP_PROTO(const char *dev_name, const char *state, u32 rate),\n+\tTP_ARGS(dev_name, state, rate),\n+\n+\tTP_STRUCT__entry(\n+\t\t__string(dev_name, dev_name)\n+\t\t__string(state, state)\n+\t\t__field(u32, rate)\n+\t),\n+\n+\tTP_fast_assign(\n+\t\t__assign_str(dev_name);\n+\t\t__assign_str(state);\n+\t\t__entry->rate = rate;\n+\t),\n+\n+\tTP_printk(\"dev: %s state: %s rate: %s\",\n+\t\t__get_str(dev_name), __get_str(state),\n+\t\t__print_symbolic(__entry->rate, RATE)\n+\t)\n+);\n+\n+#endif /* _TRACE_HW_EVENT_PCI_CONTROLLER_H */\n+\n+/* This part must be outside protection */\n+#include <trace/define_trace.h>\n", "prefixes": [ "v5", "1/3" ] }