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GET /api/patches/2215650/?format=api
{ "id": 2215650, "url": "http://patchwork.ozlabs.org/api/patches/2215650/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260325011119.287660-1-marek.vasut+renesas@mailbox.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325011119.287660-1-marek.vasut+renesas@mailbox.org>", "list_archive_url": null, "date": "2026-03-25T01:10:43", "name": "net: rswitch: Remap CPU to bus addresses using dev_phys_to_bus()", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "c389a5aa33503c73e706457c4792314a2129c77d", "submitter": { "id": 85650, "url": "http://patchwork.ozlabs.org/api/people/85650/?format=api", "name": "Marek Vasut", "email": "marek.vasut+renesas@mailbox.org" }, "delegate": { "id": 157425, "url": "http://patchwork.ozlabs.org/api/users/157425/?format=api", "username": "jforissier", "first_name": "Jerome", "last_name": "Forissier", "email": "jerome.forissier@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260325011119.287660-1-marek.vasut+renesas@mailbox.org/mbox/", "series": [ { "id": 497366, "url": "http://patchwork.ozlabs.org/api/series/497366/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497366", "date": "2026-03-25T01:10:43", "name": "net: rswitch: Remap CPU to bus addresses using dev_phys_to_bus()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497366/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215650/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215650/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=mailbox.org header.i=@mailbox.org header.a=rsa-sha256\n header.s=mail20150812 header.b=sSLHYIQ4;\n\tdkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org\n header.a=rsa-sha256 header.s=mail20150812 header.b=RO3Dw4DU;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Wed, 25 Mar 2026 02:11:27 +0100 (CET)", "from mout-p-201.mailbox.org (mout-p-201.mailbox.org [80.241.56.171])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id A393B81E18\n for <u-boot@lists.denx.de>; Wed, 25 Mar 2026 02:11:24 +0100 (CET)", "from smtp2.mailbox.org (smtp2.mailbox.org [10.196.197.2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest\n SHA256)\n (No client certificate requested)\n by mout-p-201.mailbox.org (Postfix) with ESMTPS id 4fgTPm1cy8z9tvd;\n Wed, 25 Mar 2026 02:11:24 +0100 (CET)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_RPBL_BLOCKED,RCVD_IN_VALIDITY_SAFE_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org;\n s=mail20150812; t=1774401084;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding;\n bh=n+B80JOCxb4B85qiKEuMosQJwGqMyVUP0K8cWoxNQyI=;\n b=sSLHYIQ4rL2I83efUd+MoOaLq7RA2b6G+ORjvAtgEr6YeJ2cesZRx9+w/GG/j/QBj2gWuI\n HEzhuW0B8TK++j5Ojv6fxxN4F1L6W0UhVTg3UQzcjJ137zap+JOG6vEpZ2uWUOIt2z2ZRD\n YHnTI4PHEuiF1E+fTQVq6ppj9VRLLW2sPvdpknxaXr/KnLfSUggRQ50akAVPv/TXoedPxM\n SlhkZi1nNntaB/ch+0Dk+8zck2EO1E1a+qDvZJ4Fqf/Orw/R9Xw93ha3fi12ulHRo/mkCh\n CdCkGTzLsIw3yXPOTAm1GUGdDnl4Xcej7TZ/iGYACfcr3bf9cFV4kr7j+xcd1w==", "v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org;\n s=mail20150812; t=1774401082;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding;\n bh=n+B80JOCxb4B85qiKEuMosQJwGqMyVUP0K8cWoxNQyI=;\n b=RO3Dw4DUtYCkah2JqJHQxRyBMfHhaDTY5HsyMfoc+hjAdrlTjeMjCZ7xnxXR/Pramh2Vea\n awLu2k+x/2kF/9u/q4DdLeqcvNt1L8qShC73jkbre56L3+s6LliSCPeucBkFrY0BS/cYJJ\n 9ZJR+FiNODectms3NLOz3Dq+oMW3zwRBcZLhpVmaXIdOLDKVCeZCLDBM5vcJ6SUZs9XzOt\n kaCCoW4JFfjGCsDq3JzR3y1esakPIhKOH19iy+75m5vIIc7YXj57tiGyeCNV4M/O0g/o9v\n CUavpXfspIn6/tw0kVLFqTJ9/4XTCjRfcAsbqV3TpJj5zrEcWo/MbJWKy5dk/g==" ], "From": "Marek Vasut <marek.vasut+renesas@mailbox.org>", "To": "u-boot@lists.denx.de", "Cc": "Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Andrew Goodbody <andrew.goodbody@linaro.org>,\n Hai Pham <hai.pham.ud@renesas.com>,\n Jerome Forissier <jerome.forissier@arm.com>,\n Nobuhiro Iwamatsu <iwamatsu@nigauri.org>,\n Phong Hoang <phong.hoang.wz@renesas.com>,\n Tam Nguyen <tam.nguyen.xa@renesas.com>,\n Thanh Quan <thanh.quan.xn@renesas.com>, Tom Rini <trini@konsulko.com>", "Subject": "[PATCH] net: rswitch: Remap CPU to bus addresses using\n dev_phys_to_bus()", "Date": "Wed, 25 Mar 2026 02:10:43 +0100", "Message-ID": "<20260325011119.287660-1-marek.vasut+renesas@mailbox.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-MBO-RS-ID": "888a15918140ea98528", "X-MBO-RS-META": "yiyy3dkne1ccdryuxjctcdjfbcixfptb", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Use dev_phys_to_bus() to convert CPU addresses of DMA descriptors\ninto bus addresses of DMA descriptors. This is necessary on hardware\nwhich does not have 1:1 mapping between CPU and memory addressed by\nthe DMA. This has no impact on other hardware which does not need\nthis conversion.\n\nSigned-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>\n---\nCc: Andrew Goodbody <andrew.goodbody@linaro.org>\nCc: Hai Pham <hai.pham.ud@renesas.com>\nCc: Jerome Forissier <jerome.forissier@arm.com>\nCc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>\nCc: Phong Hoang <phong.hoang.wz@renesas.com>\nCc: Tam Nguyen <tam.nguyen.xa@renesas.com>\nCc: Thanh Quan <thanh.quan.xn@renesas.com>\nCc: Tom Rini <trini@konsulko.com>\nCc: u-boot@lists.denx.de\n---\n drivers/net/rswitch.c | 80 ++++++++++++++++++++++++-------------------\n 1 file changed, 44 insertions(+), 36 deletions(-)", "diff": "diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c\nindex c51908ed8f3..52fc3edd4e0 100644\n--- a/drivers/net/rswitch.c\n+++ b/drivers/net/rswitch.c\n@@ -9,6 +9,7 @@\n \n #include <asm/io.h>\n #include <clk.h>\n+#include <cpu_func.h>\n #include <dm.h>\n #include <dm/device-internal.h>\n #include <dm/device_compat.h>\n@@ -23,6 +24,7 @@\n #include <log.h>\n #include <malloc.h>\n #include <miiphy.h>\n+#include <phys2bus.h>\n \n #define RSWITCH_SLEEP_US\t1000\n #define RSWITCH_TIMEOUT_US\t1000000\n@@ -587,9 +589,11 @@ static void rswitch_bat_desc_init(struct rswitch_port_priv *priv)\n \trswitch_flush_dcache((uintptr_t)priv->bat_desc, desc_size);\n }\n \n-static void rswitch_tx_desc_init(struct rswitch_port_priv *priv)\n+static void rswitch_tx_desc_init(struct udevice *dev)\n {\n+\tstruct rswitch_port_priv *priv = dev_get_priv(dev);\n \tconst u32 desc_size = RSWITCH_NUM_TX_DESC * sizeof(struct rswitch_desc);\n+\tdma_addr_t tx_desc_ba;\n \tu64 tx_desc_addr;\n \tint i;\n \n@@ -603,21 +607,25 @@ static void rswitch_tx_desc_init(struct rswitch_port_priv *priv)\n \t/* Mark the end of the descriptors */\n \tpriv->tx_desc[RSWITCH_NUM_TX_DESC - 1].die_dt = DT_LINKFIX;\n \ttx_desc_addr = (uintptr_t)priv->tx_desc;\n-\tpriv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrl = lower_32_bits(tx_desc_addr);\n-\tpriv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrh = upper_32_bits(tx_desc_addr);\n+\ttx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)tx_desc_addr);\n+\n+\tpriv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrl = lower_32_bits(tx_desc_ba);\n+\tpriv->tx_desc[RSWITCH_NUM_TX_DESC - 1].dptrh = upper_32_bits(tx_desc_ba);\n \trswitch_flush_dcache(tx_desc_addr, desc_size);\n \n \t/* Point the controller to the TX descriptor list */\n \tpriv->bat_desc[RSWITCH_TX_CHAIN_INDEX].die_dt = DT_LINKFIX;\n-\tpriv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrl = lower_32_bits(tx_desc_addr);\n-\tpriv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrh = upper_32_bits(tx_desc_addr);\n+\tpriv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrl = lower_32_bits(tx_desc_ba);\n+\tpriv->bat_desc[RSWITCH_TX_CHAIN_INDEX].dptrh = upper_32_bits(tx_desc_ba);\n \trswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_TX_CHAIN_INDEX],\n \t\t\t sizeof(struct rswitch_desc));\n }\n \n-static void rswitch_rx_desc_init(struct rswitch_port_priv *priv)\n+static void rswitch_rx_desc_init(struct udevice *dev)\n {\n+\tstruct rswitch_port_priv *priv = dev_get_priv(dev);\n \tconst u32 desc_size = RSWITCH_NUM_RX_DESC * sizeof(struct rswitch_rxdesc);\n+\tdma_addr_t packet_ba, next_rx_desc_ba, rx_desc_ba;\n \tint i;\n \tu64 packet_addr;\n \tu64 next_rx_desc_addr;\n@@ -631,26 +639,29 @@ static void rswitch_rx_desc_init(struct rswitch_port_priv *priv)\n \t\tpriv->rx_desc[i].data.die_dt = DT_FEMPTY;\n \t\tpriv->rx_desc[i].data.info_ds = PKTSIZE_ALIGN;\n \t\tpacket_addr = (uintptr_t)priv->rx_desc[i].packet;\n-\t\tpriv->rx_desc[i].data.dptrl = lower_32_bits(packet_addr);\n-\t\tpriv->rx_desc[i].data.dptrh = upper_32_bits(packet_addr);\n+\t\tpacket_ba = dev_phys_to_bus(dev, (phys_addr_t)packet_addr);\n+\t\tpriv->rx_desc[i].data.dptrl = lower_32_bits(packet_ba);\n+\t\tpriv->rx_desc[i].data.dptrh = upper_32_bits(packet_ba);\n \n \t\tpriv->rx_desc[i].link.die_dt = DT_LINKFIX;\n \t\tnext_rx_desc_addr = (uintptr_t)&priv->rx_desc[i + 1];\n-\t\tpriv->rx_desc[i].link.dptrl = lower_32_bits(next_rx_desc_addr);\n-\t\tpriv->rx_desc[i].link.dptrh = upper_32_bits(next_rx_desc_addr);\n+\t\tnext_rx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)next_rx_desc_addr);\n+\t\tpriv->rx_desc[i].link.dptrl = lower_32_bits(next_rx_desc_ba);\n+\t\tpriv->rx_desc[i].link.dptrh = upper_32_bits(next_rx_desc_ba);\n \t}\n \n \t/* Mark the end of the descriptors */\n \tpriv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.die_dt = DT_LINKFIX;\n \trx_desc_addr = (uintptr_t)priv->rx_desc;\n-\tpriv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrl = lower_32_bits(rx_desc_addr);\n-\tpriv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrh = upper_32_bits(rx_desc_addr);\n+\trx_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)rx_desc_addr);\n+\tpriv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrl = lower_32_bits(rx_desc_ba);\n+\tpriv->rx_desc[RSWITCH_NUM_RX_DESC - 1].link.dptrh = upper_32_bits(rx_desc_ba);\n \trswitch_flush_dcache(rx_desc_addr, desc_size);\n \n \t/* Point the controller to the rx descriptor list */\n \tpriv->bat_desc[RSWITCH_RX_CHAIN_INDEX].die_dt = DT_LINKFIX;\n-\tpriv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrl = lower_32_bits(rx_desc_addr);\n-\tpriv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrh = upper_32_bits(rx_desc_addr);\n+\tpriv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrl = lower_32_bits(rx_desc_ba);\n+\tpriv->bat_desc[RSWITCH_RX_CHAIN_INDEX].dptrh = upper_32_bits(rx_desc_ba);\n \trswitch_flush_dcache((uintptr_t)&priv->bat_desc[RSWITCH_RX_CHAIN_INDEX],\n \t\t\t sizeof(struct rswitch_desc));\n }\n@@ -741,9 +752,11 @@ static int rswitch_gwca_axi_ram_reset(struct rswitch_gwca *gwca)\n \t\t\t\t\tRSWITCH_SLEEP_US, RSWITCH_TIMEOUT_US);\n }\n \n-static int rswitch_gwca_init(struct rswitch_port_priv *priv)\n+static int rswitch_gwca_init(struct udevice *dev)\n {\n+\tstruct rswitch_port_priv *priv = dev_get_priv(dev);\n \tstruct rswitch_gwca *gwca = &priv->gwca;\n+\tdma_addr_t bat_desc_ba;\n \tint ret;\n \n \tret = rswitch_gwca_change_mode(priv, GWMC_OPC_DISABLE);\n@@ -765,9 +778,11 @@ static int rswitch_gwca_init(struct rswitch_port_priv *priv)\n \t/* Setting flow */\n \twritel(GWVCC_VEM_SC_TAG, gwca->addr + GWVCC);\n \twritel(0, gwca->addr + GWTTFC);\n-\twritel(upper_32_bits((uintptr_t)priv->bat_desc) & GWDCBAC0_DCBAUP,\n+\n+\tbat_desc_ba = dev_phys_to_bus(dev, (phys_addr_t)(priv->bat_desc));\n+\twritel(upper_32_bits(bat_desc_ba) & GWDCBAC0_DCBAUP,\n \t gwca->addr + GWDCBAC0 + priv->drv_data->gwdcbac_offset);\n-\twritel(lower_32_bits((uintptr_t)priv->bat_desc),\n+\twritel(lower_32_bits(bat_desc_ba),\n \t gwca->addr + GWDCBAC1 + priv->drv_data->gwdcbac_offset);\n \twritel(GWDCC_DQT | GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_TX_CHAIN_INDEX));\n \twritel(GWDCC_BALR, gwca->addr + GWDCC(RSWITCH_RX_CHAIN_INDEX));\n@@ -844,8 +859,9 @@ static int rswitch_etha_init(struct rswitch_port_priv *priv)\n \treturn 0;\n }\n \n-static int rswitch_init(struct rswitch_port_priv *priv)\n+static int rswitch_start(struct udevice *dev)\n {\n+\tstruct rswitch_port_priv *priv = dev_get_priv(dev);\n \tstruct rswitch_etha *etha = &priv->etha;\n \tint ret;\n \n@@ -875,8 +891,8 @@ static int rswitch_init(struct rswitch_port_priv *priv)\n \t\treturn ret;\n \n \trswitch_bat_desc_init(priv);\n-\trswitch_tx_desc_init(priv);\n-\trswitch_rx_desc_init(priv);\n+\trswitch_tx_desc_init(dev);\n+\trswitch_rx_desc_init(dev);\n \n \trswitch_clock_enable(priv);\n \n@@ -886,7 +902,7 @@ static int rswitch_init(struct rswitch_port_priv *priv)\n \n \trswitch_mfwd_init(priv);\n \n-\tret = rswitch_gwca_init(priv);\n+\tret = rswitch_gwca_init(dev);\n \tif (ret)\n \t\treturn ret;\n \n@@ -897,23 +913,12 @@ static int rswitch_init(struct rswitch_port_priv *priv)\n \treturn 0;\n }\n \n-static int rswitch_start(struct udevice *dev)\n-{\n-\tstruct rswitch_port_priv *priv = dev_get_priv(dev);\n-\tint ret;\n-\n-\tret = rswitch_init(priv);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\treturn 0;\n-}\n-\n #define RSWITCH_TX_TIMEOUT_MS\t1000\n static int rswitch_send(struct udevice *dev, void *packet, int len)\n {\n \tstruct rswitch_port_priv *priv = dev_get_priv(dev);\n \tstruct rswitch_desc *desc = &priv->tx_desc[priv->tx_desc_index];\n+\tdma_addr_t bpacket = dev_phys_to_bus(dev, (phys_addr_t)packet);\n \tstruct rswitch_gwca *gwca = &priv->gwca;\n \tu32 gwtrc_index, start;\n \n@@ -923,8 +928,8 @@ static int rswitch_send(struct udevice *dev, void *packet, int len)\n \tmemset(desc, 0x0, sizeof(*desc));\n \tdesc->die_dt = DT_FSINGLE;\n \tdesc->info_ds = len;\n-\tdesc->dptrl = lower_32_bits((uintptr_t)packet);\n-\tdesc->dptrh = upper_32_bits((uintptr_t)packet);\n+\tdesc->dptrl = lower_32_bits(bpacket);\n+\tdesc->dptrh = upper_32_bits(bpacket);\n \trswitch_flush_dcache((uintptr_t)desc, sizeof(*desc));\n \n \t/* Start transmission */\n@@ -954,6 +959,7 @@ static int rswitch_recv(struct udevice *dev, int flags, uchar **packetp)\n {\n \tstruct rswitch_port_priv *priv = dev_get_priv(dev);\n \tstruct rswitch_rxdesc *desc = &priv->rx_desc[priv->rx_desc_index];\n+\tdma_addr_t dpacket;\n \tu8 *packet;\n \tint len;\n \n@@ -963,7 +969,9 @@ static int rswitch_recv(struct udevice *dev, int flags, uchar **packetp)\n \t\treturn -EAGAIN;\n \n \tlen = desc->data.info_ds & RX_DS;\n-\tpacket = (u8 *)(((uintptr_t)(desc->data.dptrh) << 32) | (uintptr_t)desc->data.dptrl);\n+\tdpacket = ((u64)(desc->data.dptrh) << 32) | (u64)(desc->data.dptrl);\n+\tpacket = (u8 *)(uintptr_t)dev_bus_to_phys(dev, dpacket);\n+\n \trswitch_invalidate_dcache((uintptr_t)packet, len);\n \n \t*packetp = packet;\n", "prefixes": [] }