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GET /api/patches/2215626/?format=api
{ "id": 2215626, "url": "http://patchwork.ozlabs.org/api/patches/2215626/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260324221624.2424092-1-Frank.Li@nxp.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324221624.2424092-1-Frank.Li@nxp.com>", "list_archive_url": null, "date": "2026-03-24T22:16:18", "name": "[v3,1/3] dt-bindings: mtd: refactor NAND bindings and add nand-controller-legacy.yaml", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "6f7520cb5245d11888e2751e27608fab9c1d0c90", "submitter": { "id": 68011, "url": "http://patchwork.ozlabs.org/api/people/68011/?format=api", "name": "Frank Li", "email": "Frank.Li@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20260324221624.2424092-1-Frank.Li@nxp.com/mbox/", "series": [ { "id": 497352, "url": "http://patchwork.ozlabs.org/api/series/497352/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=497352", "date": "2026-03-24T22:16:18", "name": "[v3,1/3] dt-bindings: mtd: refactor NAND bindings and add nand-controller-legacy.yaml", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497352/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215626/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215626/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": 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b=GcrhMVLFrSWm44CJGgW3RJfdHDIJnKsfKeIJyyG5O0oAe+IVhR/uMuFSOOikk1CRK/Iy3ncTO7DYCJXrB/Nj8mfKWdkQ9Q0jprYhjYWkkSQKEZLFl5gUo3UCp9t9jrkQWSjFmIo3QUcH/SjQpGnP40VW5xfXEiqrLJH6etHOZKdF+bp4Bp5qL5ISyNElwyMT6SFBtuVFHPO87gd7A7gYr0xCtceKmC+q4h3lDzInp6kuEuwx+p3w3e3usoJmh9AtQksFEw0QXHwL2oiYT/pE7bzvTOVnC2maBSWrwaDE+OR7ImV6BA6ALCoiZQt0X6UVmBQ9oS44Z/+SNMeV7SnBqQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass\n header.d=nxp.com; arc=none", "From": "Frank Li <Frank.Li@nxp.com>", "To": "Miquel Raynal <miquel.raynal@bootlin.com>,\n\tRichard Weinberger <richard@nod.at>,\n\tVignesh Raghavendra <vigneshr@ti.com>,\n\tRob Herring <robh@kernel.org>,\n\tKrzysztof Kozlowski <krzk+dt@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>,\n\tlinux-mtd@lists.infradead.org (open list:MEMORY TECHNOLOGY DEVICES (MTD)),\n\tdevicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE\n BINDINGS),\n\tlinux-kernel@vger.kernel.org (open list)", "Cc": "imx@lists.linux.dev,\n\tFrank Li <Frank.Li@nxp.com>", "Subject": "[PATCH v3 1/3] dt-bindings: mtd: refactor NAND bindings and add\n nand-controller-legacy.yaml", "Date": "Tue, 24 Mar 2026 18:16:18 -0400", "Message-ID": "<20260324221624.2424092-1-Frank.Li@nxp.com>", "X-Mailer": "git-send-email 2.43.0", "X-ClientProxiedBy": "SN1PR12CA0075.namprd12.prod.outlook.com\n (2603:10b6:802:20::46) To PA4PR04MB9366.eurprd04.prod.outlook.com\n (2603:10a6:102:2a9::8)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PA4PR04MB9366:EE_|PAXPR04MB8128:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6d144dda-8f85-4005-73a2-08de89f2ffa2", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n BCL:0;ARA:13230040|7416014|52116014|366016|1800799024|376014|19092799006|38350700014|13003099007|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n 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system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: The modern NAND controller binding requires NAND chips to\n be described as child nodes of the controller, for example: nand-controller\n { ... nand@0 { /* raw NAND chip properties */ }; }; However, many existing\n device trees place NAND chip properties directly within the controller\n node\n because those controllers support only a single chip. This layout is still\n widely used by older platf [...]\n Content analysis details: (-2.1 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n 0.0 T_SPF_PERMERROR SPF: test of record failed (permerror)\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]", "X-BeenThere": "linux-mtd@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-mtd/>", "List-Post": "<mailto:linux-mtd@lists.infradead.org>", "List-Help": "<mailto:linux-mtd-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n <mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "The modern NAND controller binding requires NAND chips to be described as\nchild nodes of the controller, for example:\n\n nand-controller {\n ...\n nand@0 {\n /* raw NAND chip properties */\n };\n };\n\nHowever, many existing device trees place NAND chip properties directly\nwithin the controller node because those controllers support only a single\nchip. This layout is still widely used by older platforms and by other DT\nconsumers such as U-Boot. Migrating all existing users to the new layout\nwill take time.\n\nSeveral kernel drivers, such as ams-delta.c, davinci_nand.c and\nfsmc_nand.c, still expect the legacy layout where raw NAND properties are\ndefined in the controller node.\n\nTo support both layouts during the transition:\n\n- Extract NAND chip-related properties into separate schemas\n (nand-property.yaml and raw-nand-property.yaml) from\n nand-chip.yaml and raw-nand-chip.yaml.\n- Introduce nand-controller-legacy.yaml to allow both the\n legacy and modern layouts.\n- Add a select condition in nand-controller.yaml to prevent\n node name pattern matching for fsl,* NAND controllers.\n\nKeep compatibility with existing device trees while allowing gradual\nmigration to the modern binding structure.\n\nSigned-off-by: Frank Li <Frank.Li@nxp.com>\n---\nchange in v3\n- use select: false\n- s/under/within/\n- s/property/properties/\n\ntwo problem left:\n1. about \"^nand@[a-f0-9]$\" in nand-controller-legacy.yaml\n\nallow dts to do mirgeration from legacy layout to modern layouts for different\nboards, which use the same compatible string.\n\n2. ref to mtd.yaml\n\nmtd.yaml force node name as flash@, nand@ ..., but here is parent node\nname is nand-controller@. Only two properties, duplicate these should be\nsimple and clean enough now.\n\nchange in v2\n- none\n\nchange dts layout break boot\nhttps://lore.kernel.org/imx/177281063848.253518.12995342124719933118.b4-ty@nxp.com/T/#t\n---\n .../devicetree/bindings/mtd/nand-chip.yaml | 46 +-----------\n ...oller.yaml => nand-controller-legacy.yaml} | 46 +++++-------\n .../bindings/mtd/nand-controller.yaml | 2 +\n .../{nand-chip.yaml => nand-property.yaml} | 14 +---\n .../bindings/mtd/raw-nand-chip.yaml | 74 +------------------\n ...-nand-chip.yaml => raw-nand-property.yaml} | 15 +---\n 6 files changed, 27 insertions(+), 170 deletions(-)\n copy Documentation/devicetree/bindings/mtd/{nand-controller.yaml => nand-controller-legacy.yaml} (69%)\n copy Documentation/devicetree/bindings/mtd/{nand-chip.yaml => nand-property.yaml} (89%)\n copy Documentation/devicetree/bindings/mtd/{raw-nand-chip.yaml => raw-nand-property.yaml} (94%)", "diff": "diff --git a/Documentation/devicetree/bindings/mtd/nand-chip.yaml b/Documentation/devicetree/bindings/mtd/nand-chip.yaml\nindex 609d4a4ddd80e..8800d1d072665 100644\n--- a/Documentation/devicetree/bindings/mtd/nand-chip.yaml\n+++ b/Documentation/devicetree/bindings/mtd/nand-chip.yaml\n@@ -11,6 +11,7 @@ maintainers:\n \n allOf:\n - $ref: mtd.yaml#\n+ - $ref: nand-property.yaml\n \n description: |\n This file covers the generic description of a NAND chip. It implies that the\n@@ -22,51 +23,6 @@ properties:\n description:\n Contains the chip-select IDs.\n \n- nand-ecc-engine:\n- description: |\n- A phandle on the hardware ECC engine if any. There are\n- basically three possibilities:\n- 1/ The ECC engine is part of the NAND controller, in this\n- case the phandle should reference the parent node.\n- 2/ The ECC engine is part of the NAND part (on-die), in this\n- case the phandle should reference the node itself.\n- 3/ The ECC engine is external, in this case the phandle should\n- reference the specific ECC engine node.\n- $ref: /schemas/types.yaml#/definitions/phandle\n-\n- nand-use-soft-ecc-engine:\n- description: Use a software ECC engine.\n- type: boolean\n-\n- nand-no-ecc-engine:\n- description: Do not use any ECC correction.\n- type: boolean\n-\n- nand-ecc-algo:\n- description:\n- Desired ECC algorithm.\n- $ref: /schemas/types.yaml#/definitions/string\n- enum: [hamming, bch, rs]\n-\n- nand-ecc-strength:\n- description:\n- Maximum number of bits that can be corrected per ECC step.\n- $ref: /schemas/types.yaml#/definitions/uint32\n- minimum: 1\n-\n- nand-ecc-step-size:\n- description:\n- Number of data bytes covered by a single ECC step.\n- $ref: /schemas/types.yaml#/definitions/uint32\n- minimum: 1\n-\n- secure-regions:\n- description:\n- Regions in the NAND chip which are protected using a secure element\n- like Trustzone. This property contains the start address and size of\n- the secure regions present.\n- $ref: /schemas/types.yaml#/definitions/uint64-matrix\n-\n required:\n - reg\n \ndiff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller-legacy.yaml\nsimilarity index 69%\ncopy from Documentation/devicetree/bindings/mtd/nand-controller.yaml\ncopy to Documentation/devicetree/bindings/mtd/nand-controller-legacy.yaml\nindex 28167c0cf2719..d6e612413df19 100644\n--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml\n+++ b/Documentation/devicetree/bindings/mtd/nand-controller-legacy.yaml\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n %YAML 1.2\n ---\n-$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#\n+$id: http://devicetree.org/schemas/mtd/nand-controller-legacy.yaml#\n $schema: http://devicetree.org/meta-schemas/core.yaml#\n \n title: NAND Controller Common Properties\n@@ -10,21 +10,22 @@ maintainers:\n - Miquel Raynal <miquel.raynal@bootlin.com>\n - Richard Weinberger <richard@nod.at>\n \n-description: |\n+description: >\n The NAND controller should be represented with its own DT node, and\n all NAND chips attached to this controller should be defined as\n children nodes of the NAND controller. This representation should be\n enforced even for simple controllers supporting only one chip.\n \n+ This is only for legacy nand controller, new controller should use\n+ nand-controller.yaml\n+\n properties:\n- $nodename:\n- pattern: \"^nand-controller(@.*)?\"\n \n \"#address-cells\":\n const: 1\n \n \"#size-cells\":\n- const: 0\n+ enum: [0, 1]\n \n ranges: true\n \n@@ -39,33 +40,26 @@ properties:\n minItems: 1\n maxItems: 8\n \n+ partitions:\n+ type: object\n+\n+ required:\n+ - compatible\n+\n patternProperties:\n \"^nand@[a-f0-9]$\":\n type: object\n $ref: raw-nand-chip.yaml#\n \n-required:\n- - \"#address-cells\"\n- - \"#size-cells\"\n+ \"^partition@[0-9a-f]+$\":\n+ type: object\n+ $ref: /schemas/mtd/partitions/partition.yaml#/$defs/partition-node\n+ deprecated: true\n+\n+allOf:\n+ - $ref: raw-nand-property.yaml#\n+ - $ref: nand-property.yaml#\n \n # This is a generic file other binding inherit from and extend\n additionalProperties: true\n \n-examples:\n- - |\n- nand-controller {\n- #address-cells = <1>;\n- #size-cells = <0>;\n- cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */\n-\n- /* controller specific properties */\n-\n- nand@0 {\n- reg = <0>; /* Native CS */\n- /* NAND chip specific properties */\n- };\n-\n- nand@1 {\n- reg = <1>; /* GPIO CS */\n- };\n- };\ndiff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml\nindex 28167c0cf2719..0aa61d5fa50b1 100644\n--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml\n+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml\n@@ -16,6 +16,8 @@ description: |\n children nodes of the NAND controller. This representation should be\n enforced even for simple controllers supporting only one chip.\n \n+select: false\n+\n properties:\n $nodename:\n pattern: \"^nand-controller(@.*)?\"\ndiff --git a/Documentation/devicetree/bindings/mtd/nand-chip.yaml b/Documentation/devicetree/bindings/mtd/nand-property.yaml\nsimilarity index 89%\ncopy from Documentation/devicetree/bindings/mtd/nand-chip.yaml\ncopy to Documentation/devicetree/bindings/mtd/nand-property.yaml\nindex 609d4a4ddd80e..55488a4b15487 100644\n--- a/Documentation/devicetree/bindings/mtd/nand-chip.yaml\n+++ b/Documentation/devicetree/bindings/mtd/nand-property.yaml\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n %YAML 1.2\n ---\n-$id: http://devicetree.org/schemas/mtd/nand-chip.yaml#\n+$id: http://devicetree.org/schemas/mtd/nand-property.yaml#\n $schema: http://devicetree.org/meta-schemas/core.yaml#\n \n title: NAND Chip Common Properties\n@@ -9,19 +9,12 @@ title: NAND Chip Common Properties\n maintainers:\n - Miquel Raynal <miquel.raynal@bootlin.com>\n \n-allOf:\n- - $ref: mtd.yaml#\n-\n description: |\n- This file covers the generic description of a NAND chip. It implies that the\n+ This file covers the generic properties of a NAND chip. It implies that the\n bus interface should not be taken into account: both raw NAND devices and\n SPI-NAND devices are concerned by this description.\n \n properties:\n- reg:\n- description:\n- Contains the chip-select IDs.\n-\n nand-ecc-engine:\n description: |\n A phandle on the hardware ECC engine if any. There are\n@@ -67,8 +60,5 @@ properties:\n the secure regions present.\n $ref: /schemas/types.yaml#/definitions/uint64-matrix\n \n-required:\n- - reg\n-\n # This file can be referenced by more specific devices (like spi-nands)\n additionalProperties: true\ndiff --git a/Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml b/Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml\nindex 092448d7bfc5c..792de3e3c6eee 100644\n--- a/Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml\n+++ b/Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml\n@@ -11,6 +11,7 @@ maintainers:\n \n allOf:\n - $ref: nand-chip.yaml#\n+ - $ref: raw-nand-property.yaml#\n \n description: |\n The ECC strength and ECC step size properties define the user\n@@ -31,79 +32,6 @@ properties:\n description:\n Contains the chip-select IDs.\n \n- nand-ecc-placement:\n- description:\n- Location of the ECC bytes. This location is unknown by default\n- but can be explicitly set to \"oob\", if all ECC bytes are\n- known to be stored in the OOB area, or \"interleaved\" if ECC\n- bytes will be interleaved with regular data in the main area.\n- $ref: /schemas/types.yaml#/definitions/string\n- enum: [ oob, interleaved ]\n- deprecated: true\n-\n- nand-ecc-mode:\n- description:\n- Legacy ECC configuration mixing the ECC engine choice and\n- configuration.\n- $ref: /schemas/types.yaml#/definitions/string\n- enum: [none, soft, soft_bch, hw, hw_syndrome, on-die]\n- deprecated: true\n-\n- nand-bus-width:\n- description:\n- Bus width to the NAND chip\n- $ref: /schemas/types.yaml#/definitions/uint32\n- enum: [8, 16]\n- default: 8\n-\n- nand-on-flash-bbt:\n- description:\n- With this property, the OS will search the device for a Bad\n- Block Table (BBT). If not found, it will create one, reserve\n- a few blocks at the end of the device to store it and update\n- it as the device ages. Otherwise, the out-of-band area of a\n- few pages of all the blocks will be scanned at boot time to\n- find Bad Block Markers (BBM). These markers will help to\n- build a volatile BBT in RAM.\n- $ref: /schemas/types.yaml#/definitions/flag\n-\n- nand-ecc-maximize:\n- description:\n- Whether or not the ECC strength should be maximized. The\n- maximum ECC strength is both controller and chip\n- dependent. The ECC engine has to select the ECC config\n- providing the best strength and taking the OOB area size\n- constraint into account. This is particularly useful when\n- only the in-band area is used by the upper layers, and you\n- want to make your NAND as reliable as possible.\n- $ref: /schemas/types.yaml#/definitions/flag\n-\n- nand-is-boot-medium:\n- description:\n- Whether or not the NAND chip is a boot medium. Drivers might\n- use this information to select ECC algorithms supported by\n- the boot ROM or similar restrictions.\n- $ref: /schemas/types.yaml#/definitions/flag\n-\n- nand-rb:\n- description:\n- Contains the native Ready/Busy IDs.\n- $ref: /schemas/types.yaml#/definitions/uint32-array\n-\n- rb-gpios:\n- description:\n- Contains one or more GPIO descriptor (the numper of descriptor\n- depends on the number of R/B pins exposed by the flash) for the\n- Ready/Busy pins. Active state refers to the NAND ready state and\n- should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.\n-\n- wp-gpios:\n- description:\n- Contains one GPIO descriptor for the Write Protect pin.\n- Active state refers to the NAND Write Protect state and should be\n- set to GPIOD_ACTIVE_LOW unless the signal is inverted.\n- maxItems: 1\n-\n required:\n - reg\n \ndiff --git a/Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml b/Documentation/devicetree/bindings/mtd/raw-nand-property.yaml\nsimilarity index 94%\ncopy from Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml\ncopy to Documentation/devicetree/bindings/mtd/raw-nand-property.yaml\nindex 092448d7bfc5c..f853b72426c43 100644\n--- a/Documentation/devicetree/bindings/mtd/raw-nand-chip.yaml\n+++ b/Documentation/devicetree/bindings/mtd/raw-nand-property.yaml\n@@ -1,7 +1,7 @@\n # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n %YAML 1.2\n ---\n-$id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#\n+$id: http://devicetree.org/schemas/mtd/raw-nand-property.yaml#\n $schema: http://devicetree.org/meta-schemas/core.yaml#\n \n title: Raw NAND Chip Common Properties\n@@ -9,9 +9,6 @@ title: Raw NAND Chip Common Properties\n maintainers:\n - Miquel Raynal <miquel.raynal@bootlin.com>\n \n-allOf:\n- - $ref: nand-chip.yaml#\n-\n description: |\n The ECC strength and ECC step size properties define the user\n desires in terms of correction capability of a controller. Together,\n@@ -24,13 +21,6 @@ description: |\n specify the value(s) they support.\n \n properties:\n- $nodename:\n- pattern: \"^nand@[a-f0-9]$\"\n-\n- reg:\n- description:\n- Contains the chip-select IDs.\n-\n nand-ecc-placement:\n description:\n Location of the ECC bytes. This location is unknown by default\n@@ -104,8 +94,5 @@ properties:\n set to GPIOD_ACTIVE_LOW unless the signal is inverted.\n maxItems: 1\n \n-required:\n- - reg\n-\n # This is a generic file other binding inherit from and extend\n additionalProperties: true\n", "prefixes": [ "v3", "1/3" ] }