Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2215566/?format=api
{ "id": 2215566, "url": "http://patchwork.ozlabs.org/api/patches/2215566/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260324191000.1095768-8-mmaddireddy@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324191000.1095768-8-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:09:58", "name": "[v8,7/9] PCI: tegra194: Add core monitor clock support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ff78fcbe0260c613b9485f0b8c09a96903a1bcee", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260324191000.1095768-8-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497333, "url": "http://patchwork.ozlabs.org/api/series/497333/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497333", "date": "2026-03-24T19:09:51", "name": "Enhancements to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497333/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215566/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215566/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-50971-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=eKXgT/6A;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-50971-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"eKXgT/6A\"", "smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.93.195.0", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com", "smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgKdw29kXz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 06:21:24 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 782B631CDE43\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 24 Mar 2026 19:14:12 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id A329D3CF68D;\n\tTue, 24 Mar 2026 19:11:45 +0000 (UTC)", "from SN4PR2101CU001.outbound.protection.outlook.com\n (mail-southcentralusazon11012000.outbound.protection.outlook.com\n [40.93.195.0])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id BA28D3CF691;\n\tTue, 24 Mar 2026 19:11:42 +0000 (UTC)", "from DM6PR01CA0002.prod.exchangelabs.com (2603:10b6:5:296::7) by\n DS7PR12MB8274.namprd12.prod.outlook.com (2603:10b6:8:da::13) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9745.20; Tue, 24 Mar 2026 19:11:34 +0000", "from DS3PEPF000099E0.namprd04.prod.outlook.com\n (2603:10b6:5:296:cafe::ff) by DM6PR01CA0002.outlook.office365.com\n (2603:10b6:5:296::7) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9723.31 via Frontend Transport; Tue,\n 24 Mar 2026 19:11:08 +0000", "from mail.nvidia.com (216.228.117.161) by\n DS3PEPF000099E0.mail.protection.outlook.com (10.167.17.203) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9723.19 via Frontend Transport; Tue, 24 Mar 2026 19:11:33 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 24 Mar\n 2026 12:11:08 -0700", "from mmaddireddy-ubuntu.nvidia.com (10.126.230.35) by\n rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.2562.20; Tue, 24 Mar 2026 12:11:01 -0700" ], "ARC-Seal": [ "i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774379505; cv=fail;\n b=JDuVQJtBcl17clq2vJB7AILn7xTSUUcIOnLt4zolSsQYfPFbTgRJ+5NR1OhVMi470s2idhQ6DyRL78XiNq/RQHN+kq8isVGcN9Js5uXPSV8rw0a3hAXcYV6Eldklx9QEG7UiIH9Bmr+ir3j8o01ZVF/DozoQUIrgOnh4XprYMfE=", "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=Eeqo9FwkofOHL4g3E6iDXtAYNVqaXsSKbr0ZWz5799oEi+q+JlYMkcStVHu4Mp6tVuOn5jBBCElP5M8TkpyNfwfnWrWHAqSID3KAvgYMmsqcGo7BlyJrQpVbQ3KtCVKO8ewop2kgYoqieiLdvBx4jeRgRDTYPndm//aI9hYjt1tnGP49dJ0oooTwRXZ0ERjX/GmYhc0B84D1l64vvW5to/qS0ljR3sgYmLUEESslx/aiBOsap0cbvKT4uHGf5naTCuXl2O7ynkOOXLZ1EzdQfsGEm+ow5kxLprBWmirvnEKZjQv6EMmHTkt0kkoeIn4eP9DK0Uoas/pIOVdQNhuV7A==" ], "ARC-Message-Signature": [ "i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774379505; c=relaxed/simple;\n\tbh=iigPcha1DyqmhGsBMW0N/VfFroccJWoCqdQzJENpIp4=;\n\th=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=mIDCc5oScMsuJDXX1l+c0ycorf/p25PT8NiQmOBhkga5NOjEWEsDdLbKgf/OHZFyLN666JjwEmb93mkQkNZV6eF6vIDfSzF1ScVZ9jC4ZuYiOWbans+VjOp/ybVkdhWNoTZ9opBh30LBl7MISpi2LrzrEgT/jKiEHtXwHHtxzbI=", "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=nrL9bwfXN64LpVdGTfvN4m5ASAJvwLrX9amgMlhysGs=;\n b=g2We/9PFA3JNWTVBj1hmsGix8nrZaet2KvdtFlv8AfQBwUKLqWPEspQ+/KBWzT2FyWCzwB5ZMtzz3OiS7Trj+o/3+SdiUbUGV0jlOINe3Ulqdq1eR0tN5pPUFyXJXb7kZfJ5+02kCmMTSUjF9M5tAh2mZ3IKtSUdxw+Mh/Bl7n/YA8YME1E6I8WkwrowhAtChVl9zSrCEwiQ4GLTY1V6ufRPNFKBpenHNd7noxNqEG11KN3WAAJWJo6DwRm0QNOXDbYLWDVY0AZnt0UIEWklH2jyuwRv4pUKtAJ4v2hb/EMD9ApJVh5nBd8IzN5paiuivi2SId2gbWiLEI9qCLqMaw==" ], "ARC-Authentication-Results": [ "i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=eKXgT/6A; arc=fail smtp.client-ip=40.93.195.0", "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=nrL9bwfXN64LpVdGTfvN4m5ASAJvwLrX9amgMlhysGs=;\n b=eKXgT/6AJs8c2zJ+nZ3IQQY3q65atgCikb5OULspsW3Jfgu+9CFuB0HT1zOKozPnDONgEb3gtRuZBfzm3mJYwX0ySYQLStyoBuBckra5Dztr0gV235t7p+JyPAQfB0+XKw84KEYsMVAEeK7ANglgHVOl/GNmFxve5AVCE3EZ4Be7oRg/eSXifu8YWgOqEymG2zqynrwqmimfFB7S8fipq8hwYTh2ZwRH1FTxQFIztWfYzNKjd5JAHJE3Xu52BOLRX50yz8PkS3flfzpzYJ/SGrP/D8N62gSLE2shKUKvE50fdkMCCeraDrPhHUGl4fL1dLsZdhWRHvD5zwZcAatePQ==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<kishon@kernel.org>, <arnd@arndb.de>, <gregkh@linuxfoundation.org>,\n\t<Frank.Li@nxp.com>, <den@valinux.co.jp>, <hongxing.zhu@nxp.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH v8 7/9] PCI: tegra194: Add core monitor clock support", "Date": "Wed, 25 Mar 2026 00:39:58 +0530", "Message-ID": "<20260324191000.1095768-8-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260324191000.1095768-1-mmaddireddy@nvidia.com>", "References": "<20260324191000.1095768-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS3PEPF000099E0:EE_|DS7PR12MB8274:EE_", "X-MS-Office365-Filtering-Correlation-Id": "10ccb78d-c4c0-4dd9-bfa3-08de89d92a1c", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700016|921020|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tZdva76N1KYGU/mPdjTFsu0DLHz5V/r/8tWOftSmZ5F9Mb17+pssc88Tq2YYPRyV5HaV5kiSgGHgtD7MVVM9OSEf5tFa8gFmTjRtTntWTswU/HGalk7AvH16rhwTRsXXimNRnOobBuqOxirrEIpmhRtb8aS7o+TRFLSuLoPZPast458l3J7l2iTQdx7gJ5foGgryFT5mzam67v4tNfOTkD+kMgtn8syPVJD1JZm5fx63WjExDT/GDiHX7SYicC/b9nGUq05s8zixI2/HvKygkPFRDI9IywdjN6h4Ds+qnLsjAJZ7a397uet8uEHTAY3zjysAcAPz3eh6XtNpMlb+ryr5URwVrG5uhb+myx0AhyyRB4kw2RQb96gV9LO6/LlZTDHfx4SNljrjLIOV3PKkwQFdthQLkg3cusTbFIuAHKW5nmVYEKZuDNKbUEZgi1EEtM30PTyKX5wzYDByNaRUumaGfmeUHBkGKmQ37+qW06xKWFev8iPihxE+HkQudrm6I0VW1perQwQYEO34hgh6JpkomnlBR0DoErIHeE2TrgViYd4kfTPak5z1QEbXG4T1sba53FKb4bJHW+DtfBgf4jFGVQR5tgc7L1VtMG49zgUWUQ6lS9h2Y5GFeaGQ56jQyy79uRVfp7EkfxpXCc5QRTVwm6ZbAs9Ll3EYrKZbpEGiXDtxd3PW0VoRiuGiXMrl6qrPh+AvLNNCQbHTzOcjeK2CD/H4Ck8nr/Gjg5O7GicZD92K236gsmVQYeC46J7ERK7hnmZTlHSAxBWKpsZRyqh4/ifrGClrDexlu1+Be/NJcVbOGcl/SkAphAuagGc1n", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700016)(921020)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t8U/Slt4Z1g0S8M358k9xDM8wGOw2ge6261sxdrWZHTGhs2FBfje3dP5JGl/bzgKBP6rngmN6y34HzEkXp0qX7zhepR/exlW3lnxZRkmp4Fi0JJGH55XQy0NyFjNWri+BByFMGUwIueYAgkiXyl5H+hpJF85NjnNTQDmoK6bptwdcSHcNfI1xtMVA+yg/x01zhJ3kYLc2WRVFwSdgO1HwsW4GJGpatjBNt4hGwzzXsWz1d1LEZBGBpFKxC8mEI+8D482LZXwCHsN7gCBzPxZV3CJJ3+Vl4hCuWsQEEYTHUpRrvUY9YKpt8BNxyjktMESjP9yMiwzSMg09T0iyUeeEWxorx5DSryKYQGhuRsw+q87/yy+zD9ykqr/FLk6iZGqAjdIBnlr4uSAj2Os4WwRmbvzpz11P+06CMyWGSt9kpEMJF1CJEYrm4V6/aEY/HaEQ", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2026 19:11:33.9137\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 10ccb78d-c4c0-4dd9-bfa3-08de89d92a1c", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDS3PEPF000099E0.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS7PR12MB8274" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nAdd support for Tegra PCIe core clock monitoring. Monitoring tracks rate\nchanges that may occur due to link speed changes and is useful for\ndetecting core clock changes not initiated by software. Parse the monitor\nclock from device tree and enable it when present.\n\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V8: Fix commit message\nChanges V1 -> V7: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 4527d4759e42..3278353b2c29 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -249,6 +249,7 @@ struct tegra_pcie_dw {\n \tstruct resource *atu_dma_res;\n \tvoid __iomem *appl_base;\n \tstruct clk *core_clk;\n+\tstruct clk *core_clk_m;\n \tstruct reset_control *core_apb_rst;\n \tstruct reset_control *core_rst;\n \tstruct dw_pcie pci;\n@@ -945,6 +946,8 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)\n \t}\n \n \tclk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);\n+\tif (clk_prepare_enable(pcie->core_clk_m))\n+\t\tdev_err(pci->dev, \"Failed to enable core monitor clock\\n\");\n \n \treturn 0;\n }\n@@ -1017,6 +1020,12 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)\n \t\tval &= ~PCI_DLF_EXCHANGE_ENABLE;\n \t\tdw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);\n \n+\t\t/*\n+\t\t * core_clk_m is enabled as part of host_init callback in\n+\t\t * dw_pcie_host_init(). Disable the clock since below\n+\t\t * tegra_pcie_dw_host_init() will enable it again.\n+\t\t */\n+\t\tclk_disable_unprepare(pcie->core_clk_m);\n \t\ttegra_pcie_dw_host_init(pp);\n \t\tdw_pcie_setup_rc(pp);\n \n@@ -1610,6 +1619,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n \n static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)\n {\n+\tclk_disable_unprepare(pcie->core_clk_m);\n \tdw_pcie_host_deinit(&pcie->pci.pp);\n \ttegra_pcie_dw_pme_turnoff(pcie);\n \ttegra_pcie_unconfig_controller(pcie);\n@@ -2160,6 +2170,11 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)\n \t\treturn PTR_ERR(pcie->core_clk);\n \t}\n \n+\tpcie->core_clk_m = devm_clk_get_optional(dev, \"core_m\");\n+\tif (IS_ERR(pcie->core_clk_m))\n+\t\treturn dev_err_probe(dev, PTR_ERR(pcie->core_clk_m),\n+\t\t\t\t \"Failed to get monitor clock\\n\");\n+\n \tpcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,\n \t\t\t\t\t\t \"appl\");\n \tif (!pcie->appl_res) {\n@@ -2356,6 +2371,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)\n \tif (!pcie->link_state)\n \t\treturn 0;\n \n+\tclk_disable_unprepare(pcie->core_clk_m);\n \ttegra_pcie_dw_pme_turnoff(pcie);\n \ttegra_pcie_unconfig_controller(pcie);\n \n", "prefixes": [ "v8", "7/9" ] }