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GET /api/patches/2215556/?format=api
{ "id": 2215556, "url": "http://patchwork.ozlabs.org/api/patches/2215556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324191000.1095768-6-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324191000.1095768-6-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:09:56", "name": "[v8,5/9] PCI: tegra194: Enable hardware hot reset mode in Endpoint", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "514303ab0a680b12a56fa893df8e5107941846cf", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324191000.1095768-6-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497332, "url": "http://patchwork.ozlabs.org/api/series/497332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497332", "date": "2026-03-24T19:09:52", "name": "Enhancements to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497332/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215556/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215556/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13157-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<kishon@kernel.org>, <arnd@arndb.de>, <gregkh@linuxfoundation.org>,\n\t<Frank.Li@nxp.com>, <den@valinux.co.jp>, <hongxing.zhu@nxp.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH v8 5/9] PCI: tegra194: Enable hardware hot reset mode in\n Endpoint", "Date": "Wed, 25 Mar 2026 00:39:56 +0530", "Message-ID": "<20260324191000.1095768-6-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260324191000.1095768-1-mmaddireddy@nvidia.com>", "References": "<20260324191000.1095768-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": 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"\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(7416014)(376014)(36860700016)(921020)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tSNUOP/pjqRRXKBsPIIrD0k3TdWT905hznA5XKW0aKuSDZE1Ajnjq3yR+kkwkOO95gMKGzZzFlrAekqLMruBgi8co6vTLQ/J6Maua5QEbQPlJI7yrp9YXQD9vJIJHGrSImmu8slOJrozAviLGY9t4crWjv/f+D8txUTdETbBmkQx7GL1ntHNpt4WrbUFczby0Bzcn47SC19bxCejNWGkZEbqU0FvHtEn+lFaVP5/nDAoZUb4sB2sFCZzS3EUTJCmoxlwIrNc78cr0gH0N3qcqlSmg2vXIDnGr2qderN51Grp2tQhc0GxVW1i3Xyj9pJQUlt6fQSRzZID+IKdaXrMb5ADAuLimPWDyJQAsJR26B0H26aMZ9BCe7L89lplyrP5NrmTVTJHRTMNtUfBlljynST2xbNiS5+x+gl9JhUK4/dr+S0P08uVwB/kH11m8xgzn", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2026 19:11:15.3249\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9c5a5a79-5778-4508-0470-08de89d91f08", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDS2PEPF00003447.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4371" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nWhen PCIe link goes down, hardware can retrain the link and try to link up.\nTo enable this feature, program the APPL_CTRL register with hardware hot\nreset with immediate LTSSM enable mode.\n\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V1 -> V8: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++\n 1 file changed, 2 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex b312d02f8dab..4527d4759e42 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1791,6 +1791,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \tval = appl_readl(pcie, APPL_CTRL);\n \tval |= APPL_CTRL_SYS_PRE_DET_STATE;\n \tval |= APPL_CTRL_HW_HOT_RST_EN;\n+\tval &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);\n+\tval |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN << APPL_CTRL_HW_HOT_RST_MODE_SHIFT);\n \tappl_writel(pcie, val, APPL_CTRL);\n \n \tval = appl_readl(pcie, APPL_CFG_MISC);\n", "prefixes": [ "v8", "5/9" ] }