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GET /api/patches/2215540/?format=api
{ "id": 2215540, "url": "http://patchwork.ozlabs.org/api/patches/2215540/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-2-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324190755.1094879-2-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:07:42", "name": "[v8,01/14] PCI: tegra194: Fix polling delay for L2 state", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ffc2e0ccfeb1bae9b3afa2613fcdacfe44bf6b4b", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-2-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497330, "url": "http://patchwork.ozlabs.org/api/series/497330/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497330", "date": "2026-03-24T19:07:41", "name": "Fixes to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497330/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215540/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215540/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13138-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=DeW+VwBg;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<kishon@kernel.org>, <arnd@arndb.de>, <gregkh@linuxfoundation.org>,\n\t<Frank.Li@nxp.com>, <den@valinux.co.jp>, <hongxing.zhu@nxp.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH v8 01/14] PCI: tegra194: Fix polling delay for L2 state", "Date": "Wed, 25 Mar 2026 00:37:42 +0530", "Message-ID": "<20260324190755.1094879-2-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "References": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ5PEPF00000203:EE_|SA1PR12MB5616:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4282516a-f3c9-4513-83ac-08de89d8c331", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|7416014|1800799024|82310400026|376014|36860700016|921020|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\t4otOCOQiUaAc/kuVjbEhjjfwXGAztJadXURNadSsJhix6+4lTUTWSl38oqlEAzdTv0zTubb/aHcJWmjXm262RqZh+IoTkL60rjD5mIzi3+Eh45PBEv9PdzAoIlIQ1OSx2dmzM3a0tB7RsYdU+tQJX8O/295PGzImNGDpAtLEMdl/Sc7HB1AofJTw0AHuijBYQGXbk8PaONudH4G2CxmDKXkv584PKNGgfu782SXi+mdjXpSF7T1J5jhDlaWVZfJkJc3UW1ca56i11Knm5U34k4ZEtGrJnG1ZspLf3iUfTO4i5UYBehC626wUn/V5AapbgC+103dtATKj3pKfRVtckOE9U2EFHd4/7PnzAtG0nhvY1QI8NPc4SxJQ/EjH3QiUyTBp/MQQrlMRMMz4JF5RSFof9TY8Yhd4mEH1BhIeiAsqsmxkoO9gA9S7m/KoHdP7M/qWMpLerSzVqXm2dBp1T2CzjsSuba3CYjDHRc4IfH6sNVx1z0RgwSHlhoe+87nv2li6XsLGH1evTgJ1BCgMS7d+OkLlOS/oFLMT+OJsJDmRIGpulbCu3ZRNh4N8e5705xxk9X0o24J3y2RdKToOOu+N9v1QG8AOP97XAhXi3aKcyB8FK85bOb6zfkUr8vIaiigeR2hHp3mKxDhS5P/TB9X2YKm4ftRb6ocAKS4IdGgabq4eqGpAhgBo4qWnYLQ/1Yu7BOuCNhOufIIKzE3lNKrpFGxs/ZgFFs2nGTTAmVT9LAC2MMMT4vaZG05SrXQ2JbFNFmOakF0MiJ/TWON0WNd+eWwSIESj8IIk0JvQbcy5usgDHb/1GKB52y4r6guc", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(82310400026)(376014)(36860700016)(921020)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t/Apvqvv6aU5cNi13V5Qyu4n3w70oatXylXK2foZzXpb/plpY815SGwtN24I3fpvjmsrZeWmJj7ll52usdqkHENkW01qBVW2NZBIXQVMJya/d8xq2wisYrXFnC5QSs85fisplQw1KR6QRuBGqgMUDWDjsTszwKZELwu5ddEKu7ROlh/AsBBhwI8VU0nPPMpZDOUS/N7f+GdmfkNm7IKS8EsGD2ywi2aCXPN/Ck1fT7T2ZxckX8pApgj+vhsx8RHdHt2f97keDDi7MLxeMyxq6nDGYRVzI7ZfmnE+MVcWxPUaiWUfdd3c0DcI49heags27fM6LyWi8Cdn2J0AxK/DfkYzKhHQsgo5eTO/qgzghvi8dN3eANAJ8KyUJOUWkG4pvaHssUo2II9nkHSROYmGQ2CWFhwhCO522u4pgmhQFjyhNXCPBL4ViYi5q4qrY5TQN", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2026 19:08:41.3585\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4282516a-f3c9-4513-83ac-08de89d8c331", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ5PEPF00000203.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB5616" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nAs per PCIe spec r7.0, sec 5.3.3.2.1, after sending PME_Turn_Off message,\nRoot Port should wait for 1~10 msec for PME_TO_Ack message. Currently,\ndriver is polling for 10 msec with 1 usec delay which is aggressive.\nUse existing macro PCIE_PME_TO_L2_TIMEOUT_US to poll for 10 msec with\n1 msec delay. Since this function is used in non-atomic context only,\nuse non-atomic poll function.\n\nFixes: 56e15a238d92 (\"PCI: tegra: Add Tegra194 PCIe support\")\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V8: None\nChanges V6 -> V7: Use PCIE_PME_TO_L2_TIMEOUT_US instead PME_ACK_TIMEOUT\nChanges V1 -> V6: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 9 ++++-----\n 1 file changed, 4 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 0ddeef70726d..d6c6bd512b51 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -198,8 +198,6 @@\n #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK\tGENMASK(11, 8)\n #define CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT\t8\n \n-#define PME_ACK_TIMEOUT 10000\n-\n #define LTSSM_TIMEOUT 50000\t/* 50ms */\n \n #define GEN3_GEN4_EQ_PRESET_INIT\t5\n@@ -1553,9 +1551,10 @@ static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)\n \tval |= APPL_PM_XMT_TURNOFF_STATE;\n \tappl_writel(pcie, val, APPL_RADM_STATUS);\n \n-\treturn readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,\n-\t\t\t\t val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,\n-\t\t\t\t 1, PME_ACK_TIMEOUT);\n+\treturn readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,\n+\t\t\t\t val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,\n+\t\t\t\t PCIE_PME_TO_L2_TIMEOUT_US/10,\n+\t\t\t\t PCIE_PME_TO_L2_TIMEOUT_US);\n }\n \n static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n", "prefixes": [ "v8", "01/14" ] }