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GET /api/patches/2215534/?format=api
{ "id": 2215534, "url": "http://patchwork.ozlabs.org/api/patches/2215534/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324191000.1095768-2-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324191000.1095768-2-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:09:52", "name": "[v8,1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fa3b070892c12ab214e8b6d0db1ae6656b482c77", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324191000.1095768-2-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497332, "url": "http://patchwork.ozlabs.org/api/series/497332/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497332", "date": "2026-03-24T19:09:52", "name": "Enhancements to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497332/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215534/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215534/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13153-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=bOG9psJ7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<kishon@kernel.org>, <arnd@arndb.de>, <gregkh@linuxfoundation.org>,\n\t<Frank.Li@nxp.com>, <den@valinux.co.jp>, <hongxing.zhu@nxp.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH v8 1/9] PCI: tegra194: Drive CLKREQ# signal low explicitly", "Date": "Wed, 25 Mar 2026 00:39:52 +0530", "Message-ID": "<20260324191000.1095768-2-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260324191000.1095768-1-mmaddireddy@nvidia.com>", "References": "<20260324191000.1095768-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF00003444:EE_|MN2PR12MB4191:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f92cf6bd-ffb3-4fb5-c819-08de89d90eeb", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|7416014|376014|36860700016|82310400026|1800799024|56012099003|22082099003|18002099003|921020;", "X-Microsoft-Antispam-Message-Info": "\n\tnrHcVzIY+o2qaI3wieGUopWZSv6I8pa9vKsrJOgS+22TitiCJVAugZ7Nw+m/PuLMPSOssZ7eB72FqsE6vkK5+eWHF+HXYLH+wx22zvCdHZDIhSZyzxZLdXbJRjdoGEgHCaBckcjGJp0bDKWN7TB3po6ASN3sJNkQC509gPavZWr/I8ZhiIWOpcwPFi8HJklVU93rAXmSrfhZJbM47G8pICEUH5LRvbjtWZM0BW6C9AAAOv8KEZcfWk3Q+QNmXE5jEpjZl5mIBcOuzwzPMB71RjLoWhYlx1ulTAp5WGBWIgsOxr5XYNGYFhJwQRxXmxbZygilt3FibcRrCiH3gxlhUJrWXs7ah+1+EEQkFp5+cl2FKlNweOH9sCx4AKS3YlKaAAmg0X1ao5S23RX538g7TSZUxy41ddA2VaoH736jH5+UDSnwymzmYMo0hYGivWhuNCvehqWOsH+ZoceJhQAfBbctPcxsYAOKR5HZp7RRDRQLaTZl59YN6VZwfpaQZqUTkk/emw7ChlHnav4zmF2U8jvaRKZG2T0aPGJ9TcCxyflcUNQlOy6ZY4QP94faYmEz2hulBAsdEcX0YXmZJ5U+TA0ks+5Po1lBOQ7ZhW3Qys7kPpUoUuzxNxJLI//JDGFHjbwVjDlI/m+ieaIsENLqmUCMXZxPHpIVP466Gy4G5ep8szY41YIa8QzVnc+Yd5nuF0mNq41MawyJtYG8prH7eHkVz08FVbcXm6Ejc70wwzbJy02jWot0V5Wo4GrwDpK/hq19IvHHw+AEgOz+K9BsWVNtNauk5oK9ODbJykm9qz+B4AgVZQnml7+gUVPerxGu", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700016)(82310400026)(1800799024)(56012099003)(22082099003)(18002099003)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tvTyb1YVH/jx3GZXNuo+IakJz+pWhBHCiN+31sTReUIP043a5NOteCnDFV7ht5HHSiWPivppyvdH6+To45GWLEEXZO3rphiIsAECXQkHi4QP/IdjRNWyGLng4d4ex/OFdbcA1Z2XCI2mk1PzViAcGAPT/Uo+OnTSrNZHfaexS5Gmb7ZAzw8wqHRvy7omL7Xv0g+S+/3vLwqW0JqEk5fjpAIfl4sXdl8ZTaWRw5/9DWzeN5RfgpND8DE9L67XnhKaaZPC92ex9gGCxJRIyxQpCVvoE0gu7sC+im2zVakceMzmev/6Wb/7Olu0c3jZP+YXmkdgu/6pRPvvlHuWL8xM3rxYQENvJMOflzS3N1J+4Le9lST1qkSyHSzWVPhY549zYdNOkqEpHLx3rJYpNsAHQlv9Oxh+sgVdTx3m2o5rOMUifc0l2Y4ZMOPCyL0CwVf0V", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2026 19:10:48.3130\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f92cf6bd-ffb3-4fb5-c819-08de89d90eeb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDS2PEPF00003444.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4191" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nThe Root Port's CLKREQ# signal is shared with a downstream PCIe switch and\nthe endpoints behind it. By default, APPL_PINMUX_CLKREQ_OVERRIDE only\noverrides the CLKREQ# input to the controller (so REFCLK is enabled\ninternally); it does not drive the CLKREQ# output pin low. Some PCIe\nswitches (e.g. Broadcom PCIe Gen4) forward the Root Port's CLKREQ# to their\ndownstream side and expect it to be driven low for REFCLK, even when the\nswitch does not support CLK-PM or ASPM-L1SS. Without driving the output\npin low, link-up can fail between the switch and endpoints.\n\nClear APPL_PINMUX_CLKREQ_DEFAULT_VALUE so the CLKREQ# output pad is\nexplicitly driven low. That makes the shared CLKREQ# line low on the wire\nand avoids link-up issues with such switches.\n\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V6 -> V8: Fix commit message\nChanges V1 -> V6: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 2 ++\n 1 file changed, 2 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex b497b178bb7e..c823285368f5 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -44,6 +44,7 @@\n #define APPL_PINMUX_CLKREQ_OVERRIDE\t\tBIT(3)\n #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN\tBIT(4)\n #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE\tBIT(5)\n+#define APPL_PINMUX_CLKREQ_DEFAULT_VALUE\tBIT(13)\n \n #define APPL_CTRL\t\t\t\t0x4\n #define APPL_CTRL_SYS_PRE_DET_STATE\t\tBIT(6)\n@@ -1428,6 +1429,7 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,\n \t\tval = appl_readl(pcie, APPL_PINMUX);\n \t\tval |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;\n \t\tval &= ~APPL_PINMUX_CLKREQ_OVERRIDE;\n+\t\tval &= ~APPL_PINMUX_CLKREQ_DEFAULT_VALUE;\n \t\tappl_writel(pcie, val, APPL_PINMUX);\n \t}\n \n", "prefixes": [ "v8", "1/9" ] }