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GET /api/patches/2215533/?format=api
{ "id": 2215533, "url": "http://patchwork.ozlabs.org/api/patches/2215533/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-15-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324190755.1094879-15-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:07:55", "name": "[v8,14/14] PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f4c6c194004655c55739b152d1459b47d6812055", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-15-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497330, "url": "http://patchwork.ozlabs.org/api/series/497330/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497330", "date": "2026-03-24T19:07:41", "name": "Fixes to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497330/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215533/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215533/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13151-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=sNm/xEan;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<kishon@kernel.org>, <arnd@arndb.de>, <gregkh@linuxfoundation.org>,\n\t<Frank.Li@nxp.com>, <den@valinux.co.jp>, <hongxing.zhu@nxp.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH v8 14/14] PCI: tegra194: Fix CBB timeout caused by DBI access\n before core power-on", "Date": "Wed, 25 Mar 2026 00:37:55 +0530", "Message-ID": "<20260324190755.1094879-15-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "References": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN2PEPF000044AC:EE_|SA3PR12MB9227:EE_", "X-MS-Office365-Filtering-Correlation-Id": "1298df4f-9df2-4eda-138e-08de89d8f6c9", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|376014|7416014|36860700016|82310400026|1800799024|921020|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\thSjlS3IMvT12hF9TahsDl03H99YNVQ5GgkECcRVDemnqVd9pPIRPZSglIuUxeuDw5IIIG1J2XZ8RsdOsARfPlQBC3ijk6mtX+yZqkF63TcpHVkJsq+LxWri9oIxjku3R6vbK/cbnN5uMNzUwW/q2SlErPd6R6LMB50NE5ciMZvNEiaBucMiTRp7AYc5vCrr2CyV7VYvkS0keGQfCuqWV6dDRVyUzAbVYpkaHBijiwE6SqSwFA/Tu3WI2edQbIoIclYVEWNL6F409uPYx8ASABu9Qqjd6ecHNfHhjLk1YLSJ7R1fNcigxxcRO+++ppkvMzCLAmjDxUtfN5T8zlkuLqals24fPtj1q8TRvdooUx/VT9t+Qos2EbrN93s7A/KNzY2BFhabjxDzDPyZ/5sRVtwEgTcj6bcEdtCgy2beJFWRxBNWpmPMc/FuV+8XLhvTlNsE/OZwRYAM/FAwH/xpbWlCKkOltu3OK7Y0yfIWbwSNGrchw3fdPLs7Q0Lw6yDZQYcL6ZAMjX1fHwQ3KzMy6DKfoSEd8PqwTi0wa7PRj/o3L5Dkgc+wh5yzGlUG/HIoV72ETzMLpPVoyLjgrocU72PY3cWaV02Ye8865vScHEbZiBLkVcCaGiU3jYd32zIgJ7sIQ3T3R1Z2fpVly6CtwPJoNtVa+BARBzrNrLUtzE1yN7REC2tBTHCc7nDyz90GJZdqSS1T74DaCtPq8hA6OMVd5baP5i6ugPyBcIEqFJbw2oou6j4z32QhjL+LGHfhuIQ9e3j4TAsF2PRe8e1mUqxsjuEkWEiYxoRkLWVzqTf19BKVEN/D5VmE/+yed11LD", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(36860700016)(82310400026)(1800799024)(921020)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t1lYO3P4+8MX1Ssp1JXBhd4BSv/6sVBx/QO4c6/D5aXxsSmcMN+5gaQ/A6+hTt1AMrLmUuben+lrJfF+45ml2TPM1ZELAAJcfTdhDCR+aJMknW45dGes032y+zF/hZ/G+H/zIEllPVo0PgoZYsXqusktP0pEgXh67MS54/wWIz8iZzMVLuE4VHeF4JOYiLcpQK/X58h/SIJkKUl7+dkxSPC+rNKz9iJ69opurbvUFKxBjL+PQFwg1ZBjzaaf8g/KJvt75bDUNSrHUgDPOUbMQAaKaBuEt3nskT0OiZHUaqCIgasJ6jHLOCToRqvUyIVENaIHDO2k+zGgdPDrqC363PAUjoGaOjDy+7YjjTQRyDPWkSc38tWJUp9NDYqDyu4hByxlI078nidiYQQwWzKx7plAO1b3LOhyx1216HXuXMnlHYqvKX50eWkjj08wAnuua", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2026 19:10:07.7604\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1298df4f-9df2-4eda-138e-08de89d8f6c9", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBN2PEPF000044AC.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA3PR12MB9227" }, "content": "When PERST# is deasserted twice (assert -> deassert -> assert -> deassert),\na CBB (Control Backbone) timeout occurs at DBI register offset 0x8bc\n(PCIE_MISC_CONTROL_1_OFF). This happens because pci_epc_deinit_notify()\nand dw_pcie_ep_cleanup() are called before reset_control_deassert() powers\non the controller core.\n\nThe call chain that causes the timeout:\n pex_ep_event_pex_rst_deassert()\n pci_epc_deinit_notify()\n pci_epf_test_epc_deinit()\n pci_epf_test_clear_bar()\n pci_epc_clear_bar()\n dw_pcie_ep_clear_bar()\n __dw_pcie_ep_reset_bar()\n dw_pcie_dbi_ro_wr_en() <- Accesses 0x8bc DBI register\n reset_control_deassert(pcie->core_rst) <- Core powered on HERE\n\nThe DBI registers, including PCIE_MISC_CONTROL_1_OFF (0x8bc), are only\naccessible after the controller core is powered on via\nreset_control_deassert(pcie->core_rst). Accessing them before this point\nresults in a CBB timeout because the hardware is not yet operational.\n\nFix this by moving pci_epc_deinit_notify() and dw_pcie_ep_cleanup() to\nafter reset_control_deassert(pcie->core_rst), ensuring the controller is\nfully powered on before any DBI register accesses occur.\n\nFixes: 40e2125381dc (\"PCI: tegra194: Move controller cleanups to pex_ep_event_pex_rst_deassert()\")\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nReviewed-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V1 -> V8: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex c7cae3a004ec..b497b178bb7e 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1749,10 +1749,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \t\tgoto fail_phy;\n \t}\n \n-\t/* Perform cleanup that requires refclk */\n-\tpci_epc_deinit_notify(pcie->pci.ep.epc);\n-\tdw_pcie_ep_cleanup(&pcie->pci.ep);\n-\n \t/* Clear any stale interrupt statuses */\n \tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);\n \tappl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);\n@@ -1822,6 +1818,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \n \treset_control_deassert(pcie->core_rst);\n \n+\t/* Perform cleanup that requires refclk and core reset deasserted */\n+\tpci_epc_deinit_notify(pcie->pci.ep.epc);\n+\tdw_pcie_ep_cleanup(&pcie->pci.ep);\n+\n \tval = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);\n \tval &= ~PORT_LOGIC_SPEED_CHANGE;\n \tdw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);\n", "prefixes": [ "v8", "14/14" ] }