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GET /api/patches/2215532/?format=api
{ "id": 2215532, "url": "http://patchwork.ozlabs.org/api/patches/2215532/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-14-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324190755.1094879-14-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:07:54", "name": "[v8,13/14] PCI: tegra194: Disable L1.2 capability of Tegra234 EP", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "22feb91f8e12c5e7156c35f5526bd6274f0f1893", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-14-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497330, "url": "http://patchwork.ozlabs.org/api/series/497330/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497330", "date": "2026-03-24T19:07:41", "name": "Fixes to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497330/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215532/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215532/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13150-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=q2kRI4w0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<kishon@kernel.org>, <arnd@arndb.de>, <gregkh@linuxfoundation.org>,\n\t<Frank.Li@nxp.com>, <den@valinux.co.jp>, <hongxing.zhu@nxp.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH v8 13/14] PCI: tegra194: Disable L1.2 capability of Tegra234\n EP", "Date": "Wed, 25 Mar 2026 00:37:54 +0530", "Message-ID": "<20260324190755.1094879-14-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "References": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN2PEPF000044A8:EE_|BL1PR12MB5729:EE_", "X-MS-Office365-Filtering-Correlation-Id": "1489991c-fea9-46da-0043-08de89d8f2d8", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|921020|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tjNBeXu7Hh98GspUQsSF9+2VZdNfLbstxRasISn32dVgxFMsxc4LpsVKcSN1+vP96MPbkOXUI1ekO98Z5HsRKjQf1AcFSkADg4wgEIcYzE4VvykE6JGUnLuSUcu8A463HD6RzSxrzOr2cRMMzWra+Pn2qg/3FSkNUfisT3fIWMOynyQbFUlTA/+/qmSMHa7AQLm+O7UybkgrTsVYJkuNuSCKBKSimAnKN2g7NrCjf2gKQkHoZec2nAd87VjuNOvLskzPVsOR4BofFevQJPML9mFE1Xkq36nlH/Dj8VZS5jHVz6ux3Jbc2BpukT9qtc5jq2tqDvtdunEi0Rtg3Wg2T64F0Q70oC5H85GtiK7Xj8klrZxTNBXoDcjQ2bUt0drbyaDOH3/TgiRFR+Xow5m11531/ikSbCzzBazjABCK5KdN1kdvKXc+Ec4augk360q9/+hcy+dq55AmLklzE8xqHX3TuvtYjT+in+DGjD8P4hZlhxyB1rEXOO9PKnSkBL5ZxgRDUK2Tb807yeB88Gd5KAvNnXTY+C2ZnwQ0RTOCnjujkDBubBo8bD5PPB7SDiU0cNq0lUlysBo8fAR2mMYos8xe1HFiQLBv3E3v+5t+GPvDUDvT+97UXUUofIVvIf5swPSaNjKwmGC4JTapnXwrbfmR0zEAhxpaBxGTmlAde2vaVAjlMT3rKswVWtHQTAe72CU3gbPnNgDP7LJymMRU6twedD8FcMn41B7eizd9B7+5ZycrqoLBn7FrzQXjWTUeTHvYm0uu8tbA1YyskLvjCQ3mV+fpKcbGHCK5AzMNoN+OkpF2VvqWYfujxvWwLgyDE", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tznLZ8GeqJ0OEFLchi0+ljRN07WS3CtlCHq6pyhM5Zl7UHpBkDngFmp1CFACXwimEe5iTvbklTolec65iBGmL9aTY+w/Vo02bnCftnh2G5trCIM0MVXdhY9HMHtBkKRM/PBbxV77w3EkO91OIaIXlnI658dNXg2X7wsecK/aXXYPTDrX1/jvhIXvDHvor4rHXfyr/IaFDs171j0A2rrfLnB+ToSeY6chFRFKPCQNcjTk/bJClzBHb3nBYH9+TA7lB16B9vGJGsqOCGSvEJ/gPKyDcGkZY66VP8/Sgtrs0Cxi94gDVp/YEm10FNj+Z5sWYaWCLKrMcwL4/VsmsB65fofZ+XJblMfIuib5AC2EcKxHN1xb8FHFaOCofu0mifYBTuXbBhslYpdxnEN8DCmnfnPp6tGU8Zwhi3Bx7l9ZFco2+HKyGYDTpr4C6WYEn8t42", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2026 19:10:01.1049\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1489991c-fea9-46da-0043-08de89d8f2d8", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBN2PEPF000044A8.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5729" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nWhen Tegra234 is operating in the Endpoint mode with L1.2 enabled, PCIe\nlink goes down during L1.2 exit. This is because Tegra234 is powering up\nUPHY PLL immediately without making sure that the REFCLK is stable.\nThis is causing UPHY PLL to not lock to the correct frequency and leading\nto link going down. There is no hardware fix for this, hence do not\nadvertise the L1.2 capability in the Endpoint mode.\n\nFixes: a54e19073718 (\"PCI: tegra194: Add Tegra234 PCIe support\")\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V8: Add fixes tag and move to fixes series\nChanges V1 -> V7: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 18 ++++++++++++++++++\n 1 file changed, 18 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 4cc0bdb0b9da..c7cae3a004ec 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -234,6 +234,7 @@ struct tegra_pcie_dw_of_data {\n \tbool has_sbr_reset_fix;\n \tbool has_l1ss_exit_fix;\n \tbool has_ltr_req_fix;\n+\tbool disable_l1_2;\n \tu32 cdm_chk_int_en_bit;\n \tu32 gen4_preset_vec;\n \tu8 n_fts[2];\n@@ -679,6 +680,22 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)\n \tif (pcie->supports_clkreq)\n \t\tpci->l1ss_support = true;\n \n+\t/*\n+\t * Disable L1.2 capability advertisement for Tegra234 Endpoint mode.\n+\t * Tegra234 has a hardware bug where during L1.2 exit, the UPHY PLL is\n+\t * powered up immediately without waiting for REFCLK to stabilize. This\n+\t * causes the PLL to fail to lock to the correct frequency, resulting in\n+\t * PCIe link loss. Since there is no hardware fix available, we prevent\n+\t * the Endpoint from advertising L1.2 support by clearing the L1.2 bits\n+\t * in the L1 PM Substates Capabilities register. This ensures the host\n+\t * will not attempt to enter L1.2 state with this Endpoint.\n+\t */\n+\tif (pcie->of_data->disable_l1_2 && pcie->of_data->mode == DW_PCIE_EP_TYPE) {\n+\t\tval = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP);\n+\t\tval &= ~(PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2);\n+\t\tdw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val);\n+\t}\n+\n \t/* Program L0s and L1 entrance latencies */\n \tval = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);\n \tval &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;\n@@ -2443,6 +2460,7 @@ static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {\n \t.mode = DW_PCIE_EP_TYPE,\n \t.has_l1ss_exit_fix = true,\n \t.has_ltr_req_fix = true,\n+\t.disable_l1_2 = true,\n \t.cdm_chk_int_en_bit = BIT(18),\n \t/* Gen4 - 6, 8 and 9 presets enabled */\n \t.gen4_preset_vec = 0x340,\n", "prefixes": [ "v8", "13/14" ] }