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GET /api/patches/2215526/?format=api
{ "id": 2215526, "url": "http://patchwork.ozlabs.org/api/patches/2215526/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-8-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324190755.1094879-8-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:07:48", "name": "[v8,07/14] PCI: tegra194: Disable direct speed change for Endpoint", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a04d4013b6912876f635d30e137276b62e64fe01", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-8-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497330, "url": "http://patchwork.ozlabs.org/api/series/497330/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497330", "date": "2026-03-24T19:07:41", "name": "Fixes to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497330/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215526/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215526/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13144-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=pJNR6jJr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<kishon@kernel.org>, <arnd@arndb.de>, <gregkh@linuxfoundation.org>,\n\t<Frank.Li@nxp.com>, <den@valinux.co.jp>, <hongxing.zhu@nxp.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH v8 07/14] PCI: tegra194: Disable direct speed change for\n Endpoint", "Date": "Wed, 25 Mar 2026 00:37:48 +0530", "Message-ID": "<20260324190755.1094879-8-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "References": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN2PEPF000044A5:EE_|CH3PR12MB9098:EE_", "X-MS-Office365-Filtering-Correlation-Id": "53a0cedc-5aa4-48bd-a1d3-08de89d8da66", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|376014|7416014|36860700016|1800799024|921020|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\tXs3tKcKMwUXaBHDUmM8riI76Q8nq0bZczRwCrYieUnPz2qopN/CUfY7TZGw9fWdxFaaKWQmRkPcifip8pX0VwQdmiPaHl+ipvfciqsEO4eQdFTlQokd/RrxPkAUjbVA99l/E+OTTfPYwvDNA4/XSCW85r1GBLd9VrG9WXHOYESsaUeWPGkoSIT0rj/y+3+0kiSNXxvFvVFcEI9H9PqfB3oMk04/qoDoOgz3yEXt8JICGePTq0uAhEN112OyysKfquuAH7su+TnAwrYtuRtC5Jijmwwukrz2NTbOAVm5WzDqm+QYu54BPI24PGhjlwCK3suMs42drP1bKg0YgvI+8o3UGuN+NmUGQWgDuMsW/CXV3vCpiLQsXHprSBTANdj/9VIzzysFoAIbyDU7IepIcZtduWv22CTJlcrQ6hP5OspFH37pIMhL4vT7+j2eN80BD8ln1ZzntFGeA/sVHGViDYzAbXJg0T/klDY0O8X7w0kFRY5pagplxeVwlOJKESKsNCmugfxF3KtcwQDT7Qg1akRtJ5VNzx7naBWD9ovaptvLfDHi/5F1U5It8jZWMd+6jjhnunDGlu46MMC6r6wDjcUv6f31RxJ9QXtT7h7TjonFD6VMgjJDaAQ/pzF8HcjAwtGph0MTsAcqRoCUtyjWKrkIUBdMeD+aUAr2P8PsQ0fuMiogvk4NB+6GPDxMJhZj0AK7MONeUz5F9ua6rSNqlQGFw8UeOkA+9Age4F/N20s5kP20Z2OLL4iGEsmiafu4lPFZXH61y8k+JbdsBmCj/agmVFwWWCN4TIwHuhw/fd84WMWVOCo1rquayx1YKBe0B", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(36860700016)(1800799024)(921020)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tnBIrYOD+3CoWPr+QhhmItjCB8KURzYjrE0TdPIwJLZzJQ7wsWmNyzLAZWduTfhrpJgL2E3vo2MAWwImLK9s/3M7iDvDxCS/s9VfhebGqrpPnKqosj8+aQeAOeOWws/hOClwJwIZ2LfObRrWtZBS+m3albc5uZAHQR45LdE0rs84MxPJoC4jovJxY1/prfIisUhderndQiGyG6VN2YogbwDRORxMIqtEZlxMdoJD9E9UYPN72q19q9Zqes722mqrx0+pDniceAT9w2PqhRuRTI88j23uA6S+tfDChTw3njp7FYav6DvalAHXlmNSnhS9f3c4ENwjtIa5FiewPw3SPUmNCjVMzuW/97pCyRpuqTv57GENbepr/VfqPWYJ2N/J10rGmb9jYiIB5R2JMaLwYfQi3eOEDV02rjJpJndnYaI7TJvvX7UA9/s5QDqWa+eQR", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2026 19:09:20.1309\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 53a0cedc-5aa4-48bd-a1d3-08de89d8da66", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBN2PEPF000044A5.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH3PR12MB9098" }, "content": "From: Vidya Sagar <vidyas@nvidia.com>\n\nPre-silicon simulation showed the Endpoint initiating speed change after\nsecondary bus reset; the HW team recommended disabling this feature in the\nEndpoint. Disable direct speed change for the Endpoint so it does not\ninitiate speed change after physical layer link up at gen1, leaving speed\nchange ownership with the host.\n\nFixes: c57247f940e8 (\"PCI: tegra: Add support for PCIe endpoint mode in Tegra194\")\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V8: Fix commit mesaage\nChanges V1 -> V7: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++++\n 1 file changed, 4 insertions(+)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex e0b17ad3052d..0be701e58238 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1805,6 +1805,10 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)\n \n \treset_control_deassert(pcie->core_rst);\n \n+\tval = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);\n+\tval &= ~PORT_LOGIC_SPEED_CHANGE;\n+\tdw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);\n+\n \tif (pcie->update_fc_fixup) {\n \t\tval = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);\n \t\tval |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;\n", "prefixes": [ "v8", "07/14" ] }