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GET /api/patches/2215524/?format=api
{ "id": 2215524, "url": "http://patchwork.ozlabs.org/api/patches/2215524/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-6-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324190755.1094879-6-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:07:46", "name": "[v8,05/14] PCI: tegra194: Disable PERST IRQ only in Endpoint mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "edbf87e6783c3fab04891b3ee0c49d186993bfb3", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-6-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497330, "url": "http://patchwork.ozlabs.org/api/series/497330/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497330", "date": "2026-03-24T19:07:41", "name": "Fixes to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497330/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215524/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215524/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13142-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=hFzL/W8z;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "<bhelgaas@google.com>, <lpieralisi@kernel.org>, <kwilczynski@kernel.org>,\n\t<mani@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,\n\t<conor+dt@kernel.org>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<kishon@kernel.org>, <arnd@arndb.de>, <gregkh@linuxfoundation.org>,\n\t<Frank.Li@nxp.com>, <den@valinux.co.jp>, <hongxing.zhu@nxp.com>,\n\t<jingoohan1@gmail.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,\n\t<18255117159@163.com>", "CC": "<linux-pci@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com>", "Subject": "[PATCH v8 05/14] PCI: tegra194: Disable PERST IRQ only in Endpoint\n mode", "Date": "Wed, 25 Mar 2026 00:37:46 +0530", "Message-ID": "<20260324190755.1094879-6-mmaddireddy@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "References": "<20260324190755.1094879-1-mmaddireddy@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ5PEPF00000204:EE_|DM4PR12MB7597:EE_", "X-MS-Office365-Filtering-Correlation-Id": "bc776114-1393-4743-1073-08de89d8d18a", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|921020|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tbibbATyt6e4WN2hvwWh/xtjRovVXh6Wy/YuovaCGYp1gYA8pzv86v6qBGpdWAD+LTs/SKHUrvLqna0U0FzIzeef7EocEmR7YQpIRWvLYbuG+6NYW99I16HWPtOSh1AoDn8rVaGVq2Tu58+qiin79ichXITFPKcjASwsuy23bbd7RIndQCuz1mQ/xGLyLKwcL1EjloK9cBfkr3+CJngNq47YTEf8RGsaWmUdP/GBoruex8R+uAPqacrmawiDdL/g36VnIhqhiaHlxhIi02lRzp2iNP3y1WPXPXO44clpyLEj1+JVj1QE4UG1MH6I0SXaGlwjVwaoFlMAGblIGIQC7UikPid+LFjUfTKfxrcl+U9MWg2Vkz/xhS8w45VinQByKQ2Hs/4qVP4Y/maN703hd19j/zROKY/MMS/EJ7nWMOu5oXk00Q2eOSvG+EWF6t/5mTYBk+ChgyCNj2DdVBGaWkJ0rsjyZcE+ygfrHNoo5VgxpV6BL3KHOnb5MRewWHEDBIcibPIxa4skkvb2hH1SqTxvKD4ODMs9amW94/ovEkzPEBw+Ak1iSfAfvts9ba9w7077ZZbTlTTGl8LhKIM0ev4GQdMs4NQ6T9CuoQjzQRRAiM1mdSIk7ZbuSYA4bKhWZ0bRgn98zR6HWKPa1Q/OCjHILH0x/or9byrQVyYhi31ZYHBttCjUzL2p6R3CZDEcaAkb3g7/XLhvcrTU1kb2fvAa3avzyPDNlcSt+NYy9Y1DTTePEyN5cM2nKsmSf7bSI/ug30XV72zEOKRu//u1KRlM5F5fW5uKRPRFlxOYFWIHA7ZTUu4Fb2SP2mfBDPQ/U", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t8TB8bmGYTeWDntZu5w+y0xsWb1Orx7vtYW19k2rxjZiUwu5x2XN1L+A2cO/AYq115YHQAnCi+ohaz57dtbHGr2Efa3meUKD9j4V+HYurNcF0LTGJdzPR7KR1c8L7wIDQq3kwrTq5+jbDCiV5tKUPMBexhmkHp7ERLH2cJ7WlG/XFsdda9NUlwpr+beZNMx/GNe1eZ+bHUJX7eJP7PRotva7NMv5tzZBfzDxefDgCaC3rrAVKZJ84j3ziLc4WfFbEhpJbjRG7oUls1dGdNNJ3RPFW6AB+g02y018JVplH1+tu9OwIZ2yn3Kcaa3pz27+7rf5u/7Pqt8wFDxNkcm5TbxExKmn6oHu4s5/nGM+iHwLCOngkYmES9wpfOA6wzxdkOhPROaNYvT8QV85I+9V53axTGYq1MHTPCLWlv6TDCRYVj/5muoiDg/lVJH4XrJtL", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Mar 2026 19:09:05.4347\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bc776114-1393-4743-1073-08de89d8d18a", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSJ5PEPF00000204.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB7597" }, "content": "The PERST (PERST#) GPIO interrupt is only registered when the controller\nis operating in Endpoint mode. In Root Port mode, the PERST GPIO is\nconfigured as an output to control downstream devices, and no interrupt\nis registered for it.\n\nCurrently, tegra_pcie_dw_stop_link() unconditionally calls disable_irq()\non pex_rst_irq, which causes issues in Root Port mode where this IRQ is\nnot registered.\n\nFix this by only disabling the PERST IRQ when operating in Endpoint mode,\nwhere the interrupt is actually registered and used to detect PERST\nassertion/deassertion from the host.\n\nFixes: c57247f940e8 (\"PCI: tegra: Add support for PCIe Endpoint mode in Tegra194\")\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nReviewed-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V1 -> V8: None\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 7e15597df6c1..f3428fd3345c 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1025,7 +1025,8 @@ static void tegra_pcie_dw_stop_link(struct dw_pcie *pci)\n {\n \tstruct tegra_pcie_dw *pcie = to_tegra_pcie(pci);\n \n-\tdisable_irq(pcie->pex_rst_irq);\n+\tif (pcie->of_data->mode == DW_PCIE_EP_TYPE)\n+\t\tdisable_irq(pcie->pex_rst_irq);\n }\n \n static const struct dw_pcie_ops tegra_dw_pcie_ops = {\n", "prefixes": [ "v8", "05/14" ] }