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GET /api/patches/2215522/?format=api
{ "id": 2215522, "url": "http://patchwork.ozlabs.org/api/patches/2215522/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-4-mmaddireddy@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324190755.1094879-4-mmaddireddy@nvidia.com>", "list_archive_url": null, "date": "2026-03-24T19:07:44", "name": "[v8,03/14] PCI: tegra194: Disable LTSSM after transition to detect on surprise down", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "10e45481bece43f86b757a143e55ed3f903cb8e0", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260324190755.1094879-4-mmaddireddy@nvidia.com/mbox/", "series": [ { "id": 497330, "url": "http://patchwork.ozlabs.org/api/series/497330/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497330", "date": "2026-03-24T19:07:41", "name": "Fixes to pcie-tegra194 driver", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/497330/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215522/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215522/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13140-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=fNyBwN9y;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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Do this by polling for the\ndetect state first, then clearing APPL_CTRL_LTSSM_EN in both\ntegra_pcie_dw_pme_turnoff() and pex_ep_event_pex_rst_assert().\n\nFixes: 56e15a238d92 (\"PCI: tegra: Add Tegra194 PCIe support\")\nReviewed-by: Jon Hunter <jonathanh@nvidia.com>\nTested-by: Jon Hunter <jonathanh@nvidia.com>\nSigned-off-by: Vidya Sagar <vidyas@nvidia.com>\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\nChanges V8: Split into two patches\n\n drivers/pci/controller/dwc/pcie-tegra194.c | 29 ++++++++++++----------\n 1 file changed, 16 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 5b243c006562..baee73438638 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1594,14 +1594,6 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n \t\tdata &= ~APPL_PINMUX_PEX_RST;\n \t\tappl_writel(pcie, data, APPL_PINMUX);\n \n-\t\t/*\n-\t\t * Some cards do not go to detect state even after de-asserting\n-\t\t * PERST#. So, de-assert LTSSM to bring link to detect state.\n-\t\t */\n-\t\tdata = readl(pcie->appl_base + APPL_CTRL);\n-\t\tdata &= ~APPL_CTRL_LTSSM_EN;\n-\t\twritel(data, pcie->appl_base + APPL_CTRL);\n-\n \t\terr = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, data,\n \t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||\n \t\t\t((data & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||\n@@ -1610,6 +1602,14 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)\n \t\t\tLTSSM_DELAY_US, LTSSM_TIMEOUT_US);\n \t\tif (err)\n \t\t\tdev_info(pcie->dev, \"LTSSM state: 0x%x detect timeout: %d\\n\", data, err);\n+\n+\t\t/*\n+\t\t * Deassert LTSSM state to stop the state toggling between\n+\t\t * polling and detect.\n+\t\t */\n+\t\tdata = readl(pcie->appl_base + APPL_CTRL);\n+\t\tdata &= ~APPL_CTRL_LTSSM_EN;\n+\t\twritel(data, pcie->appl_base + APPL_CTRL);\n \t}\n \t/*\n \t * DBI registers may not be accessible after this as PLL-E would be\n@@ -1683,11 +1683,6 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)\n \tif (pcie->ep_state == EP_STATE_DISABLED)\n \t\treturn;\n \n-\t/* Disable LTSSM */\n-\tval = appl_readl(pcie, APPL_CTRL);\n-\tval &= ~APPL_CTRL_LTSSM_EN;\n-\tappl_writel(pcie, val, APPL_CTRL);\n-\n \tret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,\n \t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_QUIET) ||\n \t\t((val & APPL_DEBUG_LTSSM_STATE_MASK) == LTSSM_STATE_DETECT_ACT) ||\n@@ -1698,6 +1693,14 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)\n \tif (ret)\n \t\tdev_info(pcie->dev, \"LTSSM state: 0x%x detect timeout: %d\\n\", val, ret);\n \n+\t/*\n+\t * Deassert LTSSM state to stop the state toggling between\n+\t * polling and detect.\n+\t */\n+\tval = appl_readl(pcie, APPL_CTRL);\n+\tval &= ~APPL_CTRL_LTSSM_EN;\n+\tappl_writel(pcie, val, APPL_CTRL);\n+\n \treset_control_assert(pcie->core_rst);\n \n \ttegra_pcie_disable_phy(pcie);\n", "prefixes": [ "v8", "03/14" ] }