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GET /api/patches/2215418/?format=api
{ "id": 2215418, "url": "http://patchwork.ozlabs.org/api/patches/2215418/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-7-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324151111.237411-7-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-24T15:11:06", "name": "[PULL,06/11] hw/arm/smmuv3-accel: Change \"ril\" property type to OnOffAuto", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "30bcd96c49241fd11924856f8e7751583c05ddd5", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-7-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497302, "url": "http://patchwork.ozlabs.org/api/series/497302/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497302", "date": "2026-03-24T15:11:00", "name": "[PULL,01/11] target/arm: fix s2prot not set for two-stage PMSA translations", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497302/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215418/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215418/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=zvbyXcbQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgD725zRNz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 02:12:46 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w53Pk-0000lJ-MK; Tue, 24 Mar 2026 11:11:28 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Ph-0000hv-P3\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:25 -0400", "from mail-wr1-x431.google.com ([2a00:1450:4864:20::431])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Pf-0005DI-FK\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:24 -0400", "by mail-wr1-x431.google.com with SMTP id\n ffacd0b85a97d-43b3d9d0695so5025473f8f.0\n for <qemu-devel@nongnu.org>; Tue, 24 Mar 2026 08:11:23 -0700 (PDT)", "from lanath.. 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The 'auto'\nvalue is not implemented, as this commit is meant to set the property\nto the correct type and avoid breaking JSON/QMP when the auto mode is\nintroduced. A future patch will implement resolution of the 'auto'\nvalue to match the host SMMUv3 RIL support.\n\nThe conversion of the RIL property type to OnOffAuto is an\nincompatible change for JSON/QMP when a bool value is expected for\n\"ril\", but the \"ril\" property is new in 11.0 and this patch is\nsubmitted as a fix to the property type.\n\nFixes: bd715ff5bda9 (\"hw/arm/smmuv3-accel: Add a property to specify RIL support\")\nTested-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nTested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nAcked-by: Markus Armbruster <armbru@redhat.com>\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\nMessage-id: 20260323182454.1416110-4-nathanc@nvidia.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/smmuv3-accel.c | 6 ++++--\n hw/arm/smmuv3.c | 11 ++++++++---\n include/hw/arm/smmuv3.h | 2 +-\n 3 files changed, 13 insertions(+), 6 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex f21a6a9997..c31b64295e 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -823,8 +823,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s)\n return;\n }\n \n- /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it */\n- s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril);\n+ /* Only override RIL if user explicitly set OFF */\n+ if (s->ril == ON_OFF_AUTO_OFF) {\n+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 0);\n+ }\n \n /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */\n if (s->ats == ON_OFF_AUTO_ON) {\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex a683402a0c..ea285bdf64 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1975,9 +1975,13 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n error_setg(errp, \"ats auto mode is not supported\");\n return false;\n }\n+ if (s->ril == ON_OFF_AUTO_AUTO) {\n+ error_setg(errp, \"ril auto mode is not supported\");\n+ return false;\n+ }\n \n if (!s->accel) {\n- if (!s->ril) {\n+ if (s->ril == ON_OFF_AUTO_OFF) {\n error_setg(errp, \"ril can only be disabled if accel=on\");\n return false;\n }\n@@ -2137,7 +2141,7 @@ static const Property smmuv3_properties[] = {\n /* GPA of MSI doorbell, for SMMUv3 accel use. */\n DEFINE_PROP_UINT64(\"msi-gpa\", SMMUv3State, msi_gpa, 0),\n /* RIL can be turned off for accel cases */\n- DEFINE_PROP_BOOL(\"ril\", SMMUv3State, ril, true),\n+ DEFINE_PROP_ON_OFF_AUTO(\"ril\", SMMUv3State, ril, ON_OFF_AUTO_ON),\n DEFINE_PROP_ON_OFF_AUTO(\"ats\", SMMUv3State, ats, ON_OFF_AUTO_OFF),\n DEFINE_PROP_UINT8(\"oas\", SMMUv3State, oas, 44),\n DEFINE_PROP_UINT8(\"ssidsize\", SMMUv3State, ssidsize, 0),\n@@ -2167,7 +2171,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Enable SMMUv3 accelerator support. Allows host SMMUv3 to be \"\n \"configured in nested mode for vfio-pci dev assignment\");\n object_class_property_set_description(klass, \"ril\",\n- \"Disable range invalidation support (for accel=on)\");\n+ \"Disable range invalidation support (for accel=on). ril=auto \"\n+ \"is not supported.\");\n object_class_property_set_description(klass, \"ats\",\n \"Enable/disable ATS support (for accel=on). Please ensure host \"\n \"platform has ATS support before enabling this. ats=auto is not \"\ndiff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h\nindex ce51a5b9b4..c35e599bbc 100644\n--- a/include/hw/arm/smmuv3.h\n+++ b/include/hw/arm/smmuv3.h\n@@ -69,7 +69,7 @@ struct SMMUv3State {\n struct SMMUv3AccelState *s_accel;\n uint64_t msi_gpa;\n Error *migration_blocker;\n- bool ril;\n+ OnOffAuto ril;\n OnOffAuto ats;\n uint8_t oas;\n uint8_t ssidsize;\n", "prefixes": [ "PULL", "06/11" ] }