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GET /api/patches/2215417/?format=api
{ "id": 2215417, "url": "http://patchwork.ozlabs.org/api/patches/2215417/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-11-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324151111.237411-11-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-24T15:11:10", "name": "[PULL,10/11] hw/arm/smmuv3-accel: Change \"oas\" property type to OasMode", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "0cdee81a07ca54db81d64075cec084573d92bade", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-11-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497302, "url": "http://patchwork.ozlabs.org/api/series/497302/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497302", "date": "2026-03-24T15:11:00", "name": "[PULL,01/11] target/arm: fix s2prot not set for two-stage PMSA translations", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497302/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215417/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215417/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=KToUZIKV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgD6r5qqqz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 02:12:36 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w53Q6-0001B0-C1; Tue, 24 Mar 2026 11:11:50 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Po-0000nR-0Q\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:33 -0400", "from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Pl-0005EP-SW\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:31 -0400", "by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-439b97a8a8cso4338698f8f.1\n for <qemu-devel@nongnu.org>; Tue, 24 Mar 2026 08:11:29 -0700 (PDT)", "from lanath.. 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The\n'auto' value is not implemented, as this commit is meant to\nset the property to the correct type and avoid breaking JSON/QMP\nwhen the auto mode is introduced. A future patch will implement\nresolution of 'auto' value to match the host SMMUv3 OAS value.\n\nThe conversion of the \"oas\" property type to OnOffAuto is an\nincompatible change for JSON/QMP when a uint8_t value is expected for\n\"oas\", but this property is new in 11.0 and this patch is\nsubmitted as a fix to the property type.\n\nFixes: a015ac990fd3 (\"hw/arm/smmuv3-accel: Add property to specify OAS bits\")\nTested-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nTested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nAcked-by: Markus Armbruster <armbru@redhat.com>\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\nMessage-id: 20260323182454.1416110-8-nathanc@nvidia.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/smmuv3-accel.c | 2 +-\n hw/arm/smmuv3.c | 17 +++++++++--------\n include/hw/arm/smmuv3-common.h | 2 --\n include/hw/arm/smmuv3.h | 2 +-\n 4 files changed, 11 insertions(+), 12 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex bc6cbfebc2..65c2f44880 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -850,7 +850,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s)\n }\n \n /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */\n- if (s->oas == SMMU_OAS_48BIT) {\n+ if (s->oas == OAS_MODE_48) {\n s->idr[5] = FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48);\n }\n \ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 79018f8d66..7fead1c3cf 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1984,6 +1984,11 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n error_setg(errp, \"ssidsize auto mode is not supported\");\n return false;\n }\n+ if (s->oas != OAS_MODE_44 && s->oas != OAS_MODE_48) {\n+ error_setg(errp, \"QEMU SMMUv3 model only implements 44 and 48 bit\"\n+ \"OAS; other OasMode values are not supported\");\n+ return false;\n+ }\n \n if (!s->accel) {\n if (s->ril == ON_OFF_AUTO_OFF) {\n@@ -1994,7 +1999,7 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n error_setg(errp, \"ats can only be enabled if accel=on\");\n return false;\n }\n- if (s->oas != SMMU_OAS_44BIT) {\n+ if (s->oas > OAS_MODE_44) {\n error_setg(errp, \"OAS must be 44 bits when accel=off\");\n return false;\n }\n@@ -2012,11 +2017,6 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n return false;\n }\n \n- if (s->oas != SMMU_OAS_44BIT && s->oas != SMMU_OAS_48BIT) {\n- error_setg(errp, \"OAS can only be set to 44 or 48 bits\");\n- return false;\n- }\n-\n return true;\n }\n \n@@ -2143,7 +2143,7 @@ static const Property smmuv3_properties[] = {\n /* RIL can be turned off for accel cases */\n DEFINE_PROP_ON_OFF_AUTO(\"ril\", SMMUv3State, ril, ON_OFF_AUTO_ON),\n DEFINE_PROP_ON_OFF_AUTO(\"ats\", SMMUv3State, ats, ON_OFF_AUTO_OFF),\n- DEFINE_PROP_UINT8(\"oas\", SMMUv3State, oas, 44),\n+ DEFINE_PROP_OAS_MODE(\"oas\", SMMUv3State, oas, OAS_MODE_44),\n DEFINE_PROP_SSIDSIZE_MODE(\"ssidsize\", SMMUv3State, ssidsize,\n SSID_SIZE_MODE_0),\n };\n@@ -2180,7 +2180,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"supported.\");\n object_class_property_set_description(klass, \"oas\",\n \"Specify Output Address Size (for accel=on). Supported values \"\n- \"are 44 or 48 bits. Defaults to 44 bits\");\n+ \"are 44 or 48 bits. Defaults to 44 bits. oas=auto is not \"\n+ \"supported.\");\n object_class_property_set_description(klass, \"ssidsize\",\n \"Number of bits used to represent SubstreamIDs (SSIDs). \"\n \"A value of N allows SSIDs in the range [0 .. 2^N - 1]. \"\ndiff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h\nindex 7f0f992dfd..4609975edf 100644\n--- a/include/hw/arm/smmuv3-common.h\n+++ b/include/hw/arm/smmuv3-common.h\n@@ -342,8 +342,6 @@ REG32(IDR5, 0x14)\n FIELD(IDR5, VAX, 10, 2);\n FIELD(IDR5, STALL_MAX, 16, 16);\n \n-#define SMMU_OAS_44BIT 44\n-#define SMMU_OAS_48BIT 48\n #define SMMU_IDR5_OAS_44 4\n #define SMMU_IDR5_OAS_48 5\n \ndiff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h\nindex ddf472493d..82f18eb090 100644\n--- a/include/hw/arm/smmuv3.h\n+++ b/include/hw/arm/smmuv3.h\n@@ -72,7 +72,7 @@ struct SMMUv3State {\n Error *migration_blocker;\n OnOffAuto ril;\n OnOffAuto ats;\n- uint8_t oas;\n+ OasMode oas;\n SsidSizeMode ssidsize;\n };\n \n", "prefixes": [ "PULL", "10/11" ] }