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GET /api/patches/2215415/?format=api
{ "id": 2215415, "url": "http://patchwork.ozlabs.org/api/patches/2215415/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-12-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324151111.237411-12-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-24T15:11:11", "name": "[PULL,11/11] qemu-options.hx: Document arm-smmuv3 device's accel properties", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "4eb86efa45cf6d286f42684c9f2a828e5b489804", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-12-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497302, "url": "http://patchwork.ozlabs.org/api/series/497302/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497302", "date": "2026-03-24T15:11:00", "name": "[PULL,01/11] target/arm: fix s2prot not set for two-stage PMSA translations", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497302/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215415/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215415/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=wcOEbUCB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgD6l2ZGNz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 02:12:31 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w53Q3-0000zL-Uy; Tue, 24 Mar 2026 11:11:48 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Pq-0000qe-3H\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:37 -0400", "from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Pl-0005EU-V8\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:32 -0400", "by mail-wm1-x32c.google.com with SMTP id\n 5b1f17b1804b1-486fb439299so45578245e9.0\n for <qemu-devel@nongnu.org>; Tue, 24 Mar 2026 08:11:29 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nathan Chen <nathanc@nvidia.com>\n\nDocument arm-smmuv3 properties for setting HW-acceleration,\nRange Invalidation, and Address Translation Services support, as\nwell as setting Output Address size and Substream ID size.\n\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nTested-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nTested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\nMessage-id: 20260323182454.1416110-9-nathanc@nvidia.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n qemu-options.hx | 32 +++++++++++++++++++++++++++++++-\n 1 file changed, 31 insertions(+), 1 deletion(-)", "diff": "diff --git a/qemu-options.hx b/qemu-options.hx\nindex dbcb0155ba..21972f8326 100644\n--- a/qemu-options.hx\n+++ b/qemu-options.hx\n@@ -1279,13 +1279,43 @@ SRST\n ``aw-bits=val`` (val between 32 and 64, default depends on machine)\n This decides the address width of the IOVA address space.\n \n-``-device arm-smmuv3,primary-bus=id``\n+``-device arm-smmuv3,primary-bus=id[,option=...]``\n This is only supported by ``-machine virt`` (ARM).\n \n ``primary-bus=id``\n Accepts either the default root complex (pcie.0) or a\n pxb-pcie based root complex.\n \n+ ``accel=on|off`` (default: off)\n+ Enables guest to leverage host SMMUv3 features for acceleration.\n+ Enabling accel configures the host SMMUv3 in nested mode to support\n+ vfio-pci passthrough.\n+\n+ The following options are available when accel=on.\n+ Note: 'auto' mode is not currently supported.\n+\n+ ``ril=on|off`` (default: on)\n+ Support for Range Invalidation, which allows the SMMUv3 driver to\n+ invalidate TLB entries for a range of IOVAs at once instead of issuing\n+ separate commands to invalidate each page. Must match with host SMMUv3\n+ Range Invalidation support.\n+\n+ ``ats=on|off`` (default: off)\n+ Support for Address Translation Services, which enables PCIe devices to\n+ cache address translations in their local TLB and reduce latency. Host\n+ SMMUv3 must support ATS in order to enable this feature for the vIOMMU.\n+\n+ ``oas=val`` (supported values are 44 and 48. default: 44)\n+ Sets the Output Address Size in bits. The value set here must be less\n+ than or equal to the host SMMUv3's supported OAS, so that the\n+ intermediate physical addresses (IPA) consumed by host SMMU for stage-2\n+ translation do not exceed the host's max supported IPA size.\n+\n+ ``ssidsize=val`` (val between 0 and 20. default: 0)\n+ Sets the Substream ID size in bits. When set to a non-zero value,\n+ PASID capability is advertised to the vIOMMU and accelerated use cases\n+ such as Shared Virtual Addressing (SVA) are supported.\n+\n ``-device amd-iommu[,option=...]``\n Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU).\n Only available with ``-machine q35``, it supports the following options:\n", "prefixes": [ "PULL", "11/11" ] }