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GET /api/patches/2215413/?format=api
{ "id": 2215413, "url": "http://patchwork.ozlabs.org/api/patches/2215413/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-6-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324151111.237411-6-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-24T15:11:05", "name": "[PULL,05/11] hw/arm/smmuv3-accel: Change \"ats\" property type to OnOffAuto", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "a421114e45adf3dbdd18d34bc1efd334c0d80c07", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-6-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497302, "url": "http://patchwork.ozlabs.org/api/series/497302/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497302", "date": "2026-03-24T15:11:00", "name": "[PULL,01/11] target/arm: fix s2prot not set for two-stage PMSA translations", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497302/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215413/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215413/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=hroRSSoD;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgD6X0rXBz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 02:12:20 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w53Pk-0000kR-5z; Tue, 24 Mar 2026 11:11:28 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Pg-0000g6-Fe\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:25 -0400", "from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Pe-0005Cr-LN\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:24 -0400", "by mail-wr1-x42d.google.com with SMTP id\n ffacd0b85a97d-439af7d77f0so4121617f8f.0\n for <qemu-devel@nongnu.org>; Tue, 24 Mar 2026 08:11:21 -0700 (PDT)", "from lanath.. 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The 'auto'\nvalue is not implemented, as this commit is meant to set the property\nto the correct type and avoid breaking JSON/QMP when the auto mode is\nintroduced. A future patch will implement resolution of the 'auto'\nvalue to match the host SMMUv3 ATS support.\n\nThe conversion of the ATS property type to OnOffAuto is an\nincompatible change for JSON/QMP when a bool value is expected for\n\"ats\", but the \"ats\" property is new in 11.0 and this patch is\nsubmitted as a fix to the property type.\n\nFixes: f7f5013a55a3 (\"hw/arm/smmuv3-accel: Add support for ATS\")\nTested-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nTested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nAcked-by: Markus Armbruster <armbru@redhat.com>\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\nMessage-id: 20260323182454.1416110-3-nathanc@nvidia.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/smmuv3-accel.c | 4 +++-\n hw/arm/smmuv3.c | 17 ++++++++++++++---\n hw/arm/virt-acpi-build.c | 2 +-\n include/hw/arm/smmuv3.h | 4 +++-\n 4 files changed, 21 insertions(+), 6 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 2bb142c47f..f21a6a9997 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -827,7 +827,9 @@ void smmuv3_accel_idr_override(SMMUv3State *s)\n s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, s->ril);\n \n /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */\n- s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, s->ats);\n+ if (s->ats == ON_OFF_AUTO_ON) {\n+ s->idr[0] = FIELD_DP32(s->idr[0], IDR0, ATS, 1);\n+ }\n \n /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */\n if (s->oas == SMMU_OAS_48BIT) {\ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex 068108e49b..a683402a0c 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s)\n smmuv3_accel_idr_override(s);\n }\n \n+bool smmuv3_ats_enabled(SMMUv3State *s)\n+{\n+ return FIELD_EX32(s->idr[0], IDR0, ATS);\n+}\n+\n static void smmuv3_reset(SMMUv3State *s)\n {\n s->cmdq.base = deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS);\n@@ -1966,12 +1971,17 @@ static bool smmu_validate_property(SMMUv3State *s, Error **errp)\n }\n #endif\n \n+ if (s->ats == ON_OFF_AUTO_AUTO) {\n+ error_setg(errp, \"ats auto mode is not supported\");\n+ return false;\n+ }\n+\n if (!s->accel) {\n if (!s->ril) {\n error_setg(errp, \"ril can only be disabled if accel=on\");\n return false;\n }\n- if (s->ats) {\n+ if (s->ats == ON_OFF_AUTO_ON) {\n error_setg(errp, \"ats can only be enabled if accel=on\");\n return false;\n }\n@@ -2128,7 +2138,7 @@ static const Property smmuv3_properties[] = {\n DEFINE_PROP_UINT64(\"msi-gpa\", SMMUv3State, msi_gpa, 0),\n /* RIL can be turned off for accel cases */\n DEFINE_PROP_BOOL(\"ril\", SMMUv3State, ril, true),\n- DEFINE_PROP_BOOL(\"ats\", SMMUv3State, ats, false),\n+ DEFINE_PROP_ON_OFF_AUTO(\"ats\", SMMUv3State, ats, ON_OFF_AUTO_OFF),\n DEFINE_PROP_UINT8(\"oas\", SMMUv3State, oas, 44),\n DEFINE_PROP_UINT8(\"ssidsize\", SMMUv3State, ssidsize, 0),\n };\n@@ -2160,7 +2170,8 @@ static void smmuv3_class_init(ObjectClass *klass, const void *data)\n \"Disable range invalidation support (for accel=on)\");\n object_class_property_set_description(klass, \"ats\",\n \"Enable/disable ATS support (for accel=on). Please ensure host \"\n- \"platform has ATS support before enabling this\");\n+ \"platform has ATS support before enabling this. ats=auto is not \"\n+ \"supported.\");\n object_class_property_set_description(klass, \"oas\",\n \"Specify Output Address Size (for accel=on). Supported values \"\n \"are 44 or 48 bits. Defaults to 44 bits\");\ndiff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c\nindex 719d2f994e..591cfc993c 100644\n--- a/hw/arm/virt-acpi-build.c\n+++ b/hw/arm/virt-acpi-build.c\n@@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaque)\n \n bus = PCI_BUS(object_property_get_link(obj, \"primary-bus\", &error_abort));\n sdev.accel = object_property_get_bool(obj, \"accel\", &error_abort);\n- sdev.ats = object_property_get_bool(obj, \"ats\", &error_abort);\n+ sdev.ats = smmuv3_ats_enabled(ARM_SMMUV3(obj));\n pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);\n sbdev = SYS_BUS_DEVICE(obj);\n sdev.base = platform_bus_get_mmio_addr(pbus, sbdev, 0);\ndiff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h\nindex 26b2fc42fd..ce51a5b9b4 100644\n--- a/include/hw/arm/smmuv3.h\n+++ b/include/hw/arm/smmuv3.h\n@@ -70,7 +70,7 @@ struct SMMUv3State {\n uint64_t msi_gpa;\n Error *migration_blocker;\n bool ril;\n- bool ats;\n+ OnOffAuto ats;\n uint8_t oas;\n uint8_t ssidsize;\n };\n@@ -91,6 +91,8 @@ struct SMMUv3Class {\n ResettablePhases parent_phases;\n };\n \n+bool smmuv3_ats_enabled(struct SMMUv3State *s);\n+\n #define TYPE_ARM_SMMUV3 \"arm-smmuv3\"\n OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3)\n \n", "prefixes": [ "PULL", "05/11" ] }