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GET /api/patches/2215409/?format=api
{ "id": 2215409, "url": "http://patchwork.ozlabs.org/api/patches/2215409/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-10-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260324151111.237411-10-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-03-24T15:11:09", "name": "[PULL,09/11] qdev: Add an OasMode property type", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "eef663d6dd200b0ebc8821f340907574feed4a6c", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260324151111.237411-10-peter.maydell@linaro.org/mbox/", "series": [ { "id": 497302, "url": "http://patchwork.ozlabs.org/api/series/497302/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497302", "date": "2026-03-24T15:11:00", "name": "[PULL,01/11] target/arm: fix s2prot not set for two-stage PMSA translations", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497302/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2215409/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2215409/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ADXAkpml;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fgD6D5PY3z1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 25 Mar 2026 02:12:04 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w53Pn-0000ms-9V; Tue, 24 Mar 2026 11:11:31 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Pl-0000lX-3y\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:29 -0400", "from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1w53Pj-0005E9-FS\n for qemu-devel@nongnu.org; Tue, 24 Mar 2026 11:11:28 -0400", "by mail-wr1-x42b.google.com with SMTP id\n ffacd0b85a97d-439d8dc4ae4so4843460f8f.2\n for <qemu-devel@nongnu.org>; Tue, 24 Mar 2026 08:11:27 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-43b64717e97sm40781916f8f.35.2026.03.24.08.11.24\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 24 Mar 2026 08:11:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1774365086; x=1774969886; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=5wiSFi8wnswcXFlOefRmA6X45uTbRfHYHACuotQz0g4=;\n b=ADXAkpmlpcaBKSMRSbXCPkAc9YaKfPv3Q5Eu3p8Vl2y+vzaLhX+KyAZUq9ayhxCYk4\n dpz5NtojupISooDSpYGPrCHkUEXhlsic0IVmBOJ9M/Wd4FfOnlZNWcCFWPmflURAZKUQ\n 0UG7BQ2Jms/qblpKY9Ty28Ybz39la+3paF1SI6UN8u81FBOk0REFjVLjDZd/yrvwDnGy\n duOQM8aKwsCzGQUmIXKinIqgdFLWxPpNH1J/K7D70jg+6j+NahDcfUoUznqOe/ftR10n\n 3G2EfnPbB1s7O4LgYEi2IbQcx0dFgqahQetTv5zKvsu6DWHmU3ZQvamXTgY4gDxV08HI\n IfRA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774365086; x=1774969886;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=5wiSFi8wnswcXFlOefRmA6X45uTbRfHYHACuotQz0g4=;\n b=VYwrr4IAnDg9ghZ4QIKaqUb6YuN/p4OTSUKT8RmR1GWoJWI4I2w3J4EIJCHFj+nvao\n LzMDZFranH4wvt196fVU2kn99PPPm1+ueD3I3ZIE2Zg6yVbOV74x1tPXZRCqwboAnAYB\n bDTyIoBpn8V1CVwJ1MZ2DmPHqBrfu/qCKSNo20uAIWONqiogF8XmltA1PoLcDwjN5e7K\n KXquUhM/qzIAnqf+f7vkyQYgIsA9qDYv8I15nk38wmvJt9kxKYp6eCnX1A/E3253Mckp\n pKLx/zLui4MRWudAk76B42BynxP4jgfZ7AZSE8HbfM1BBB26ZFyjU3peatUf04ZK2BBg\n zbwQ==", "X-Gm-Message-State": "AOJu0Yz0TYJfWnj16WZkR6fU+/3FjIAmZb/Up10174vyM49e38DjQ9x3\n RycQ7zEWtt77x5ppTAdt9W4EVREOzXjN9db5z/B8rh48kKn2wRNzWwGrMFIvGhlpC3+KB1jOayM\n 4CrEJD/Y=", "X-Gm-Gg": "ATEYQzw9ieWoBk6vjGnVjYCDAERhnVldVOEjldhakATqXY5RbHSBfgSQRyPHGoIKwM+\n I5zaDz/iEfNkx06egwXNZOqJWempQoYGBzPksrd7A5VIvIasWE3cIV578yZAqU/On8987Eb1gIq\n Nawnj8iAS1PcWbKvCFnXR+gA0WKjIQ1/okX7FNPaE9A4UGTZi4FHiLGH6lM5Z/D28TikFr0wK7v\n DJ5HXMGhl64OLx7uADH2FzIMaCd69SIPCXDqXWNJTPkrLB8CVtB9gOhsElbV4Bm34igLrrQMx9k\n 8E4vB0c8doN0Vcti2tYxpJkbCsLGFkcve5HLwkSRKxv3oQinO+vtd5jJ52ksLcDZ+TK4FFtLjGj\n cTpcXa4HbjJoA3PfHUyVREn2TBFYNJqUbbcDdUXEIo4jWnMj0pT2K5gGKHuz7kyjTfeEQ93rhtk\n vinLTg0UJPrzqDRAxvVOFy4KrYe2fbl8FZk2pQZsU0XazEFuR7RWkxOhizjmlpLBYAA3mTec+Xj\n kO/jrbcwsqM/d8iv0jmIsrsi5SOf+w=", "X-Received": "by 2002:a5d:5d13:0:b0:43b:4920:56bb with SMTP id\n ffacd0b85a97d-43b6427b750mr24419103f8f.52.1774365085799;\n Tue, 24 Mar 2026 08:11:25 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 09/11] qdev: Add an OasMode property type", "Date": "Tue, 24 Mar 2026 15:11:09 +0000", "Message-ID": "<20260324151111.237411-10-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260324151111.237411-1-peter.maydell@linaro.org>", "References": "<20260324151111.237411-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42b;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nathan Chen <nathanc@nvidia.com>\n\nIntroduce a new enum type property allowing to set an Output Address\nSize. Values are auto, 32, 36, 40, 42, 44, 48, 52, and 56, where a\nvalue of N specifies an N-bit OAS.\n\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nTested-by: Eric Auger <eric.auger@redhat.com>\nTested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nAcked-by: Markus Armbruster <armbru@redhat.com>\nSigned-off-by: Nathan Chen <nathanc@nvidia.com>\nMessage-id: 20260323182454.1416110-7-nathanc@nvidia.com\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/core/qdev-properties-system.c | 13 +++++++++++\n include/hw/core/qdev-properties-system.h | 3 +++\n qapi/misc-arm.json | 28 ++++++++++++++++++++++++\n 3 files changed, 44 insertions(+)", "diff": "diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c\nindex 4aca1d4326..a805ee2e1f 100644\n--- a/hw/core/qdev-properties-system.c\n+++ b/hw/core/qdev-properties-system.c\n@@ -737,6 +737,19 @@ const PropertyInfo qdev_prop_ssidsize_mode = {\n .set_default_value = qdev_propinfo_set_default_value_enum,\n };\n \n+/* --- OasMode --- */\n+\n+QEMU_BUILD_BUG_ON(sizeof(OasMode) != sizeof(int));\n+\n+const PropertyInfo qdev_prop_oas_mode = {\n+ .type = \"OasMode\",\n+ .description = \"oas mode: auto, 32, 36, 40, 42, 44, 48, 52, 56\",\n+ .enum_table = &OasMode_lookup,\n+ .get = qdev_propinfo_get_enum,\n+ .set = qdev_propinfo_set_enum,\n+ .set_default_value = qdev_propinfo_set_default_value_enum,\n+};\n+\n /* --- Reserved Region --- */\n \n /*\ndiff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qdev-properties-system.h\nindex 4708885164..2cbea16d61 100644\n--- a/include/hw/core/qdev-properties-system.h\n+++ b/include/hw/core/qdev-properties-system.h\n@@ -15,6 +15,7 @@ extern const PropertyInfo qdev_prop_mig_mode;\n extern const PropertyInfo qdev_prop_granule_mode;\n extern const PropertyInfo qdev_prop_zero_page_detection;\n extern const PropertyInfo qdev_prop_ssidsize_mode;\n+extern const PropertyInfo qdev_prop_oas_mode;\n extern const PropertyInfo qdev_prop_losttickpolicy;\n extern const PropertyInfo qdev_prop_blockdev_on_error;\n extern const PropertyInfo qdev_prop_bios_chs_trans;\n@@ -64,6 +65,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_list;\n ZeroPageDetection)\n #define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \\\n DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMode)\n+#define DEFINE_PROP_OAS_MODE(_n, _s, _f, _d) \\\n+ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_oas_mode, OasMode)\n #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \\\n DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \\\n LostTickPolicy)\ndiff --git a/qapi/misc-arm.json b/qapi/misc-arm.json\nindex 416b4240e2..4dc66d00e5 100644\n--- a/qapi/misc-arm.json\n+++ b/qapi/misc-arm.json\n@@ -61,3 +61,31 @@\n 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',\n '10', '11', '12', '13', '14', '15', '16', '17', '18',\n '19', '20' ] } # order matters, see ssidsize_mode_to_value()\n+\n+##\n+# @OasMode:\n+#\n+# SMMUv3 Output Address Size configuration mode.\n+#\n+# @auto: derive from host IOMMU capabilities\n+#\n+# @32: 32-bit output address size\n+#\n+# @36: 36-bit output address size\n+#\n+# @40: 40-bit output address size\n+#\n+# @42: 42-bit output address size\n+#\n+# @44: 44-bit output address size\n+#\n+# @48: 48-bit output address size\n+#\n+# @52: 52-bit output address size\n+#\n+# @56: 56-bit output address size\n+#\n+# Since: 11.0\n+##\n+{ 'enum': 'OasMode',\n+ 'data': [ 'auto', '32', '36', '40', '42', '44', '48', '52', '56' ] }\n", "prefixes": [ "PULL", "09/11" ] }