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GET /api/patches/2202608/?format=api
{ "id": 2202608, "url": "http://patchwork.ozlabs.org/api/patches/2202608/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227213958.21170-5-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227213958.21170-5-philmd@linaro.org>", "list_archive_url": null, "date": "2026-02-27T21:39:58", "name": "[4/4] gdbstub: Remove @g_pos argument in gdb_register_coprocessor()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3ec95527f7279395879a51181c7c87e2c3796a69", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227213958.21170-5-philmd@linaro.org/mbox/", "series": [ { "id": 493820, "url": "http://patchwork.ozlabs.org/api/series/493820/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493820", "date": "2026-02-27T21:39:58", "name": "gdbstub: Always infer base register index from GDB XML", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/493820/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2202608/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2202608/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=QTp0ErqU;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32c;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "gdb_register_coprocessor()'s @g_pos argument is always '0',\nmeaning it is inferred from cpu->gdb_num_regs. Use instead\nfeature->base_reg, but check we don't overwrite other indexed\nregisters.\n\nThis fixes a bug with the \"power-fpu.xml\" file [*] which was\nloaded at index 70 while the base register is 71. This latent\nbug was exposed by commit 1ec0fbe2dda (\"target/ppc: Fix\nCPUClass::gdb_num_core_regs value\").\n\n[*] https://lore.kernel.org/qemu-devel/e44df309-d40d-46f0-88a8-7ac55f9a3634@fhofhammer.de/\n\nReported-by: Florian Hofhammer <florian.hofhammer@fhofhammer.de>\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n include/exec/gdbstub.h | 3 +--\n gdbstub/gdbstub.c | 16 +++++-----------\n target/arm/gdbstub.c | 21 ++++++++-------------\n target/arm/gdbstub64.c | 19 +++++++------------\n target/hexagon/cpu.c | 2 +-\n target/i386/gdbstub.c | 8 +++-----\n target/loongarch/gdbstub.c | 6 +++---\n target/m68k/helper.c | 4 ++--\n target/microblaze/cpu.c | 3 +--\n target/ppc/gdbstub.c | 11 +++++------\n target/riscv/gdbstub.c | 18 ++++++------------\n target/s390x/gdbstub.c | 15 +++++++--------\n target/sparc/gdbstub.c | 12 ++++--------\n 13 files changed, 53 insertions(+), 85 deletions(-)", "diff": "diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h\nindex 12e7b5b7282..75eb4d9c365 100644\n--- a/include/exec/gdbstub.h\n+++ b/include/exec/gdbstub.h\n@@ -35,11 +35,10 @@ void gdb_init_cpu(CPUState *cpu);\n * @set_reg - set function (gdb modifying)\n * @num_regs - number of registers in set\n * @xml - xml name of set\n- * @gpos - non-zero to append to \"general\" register set at @gpos\n */\n void gdb_register_coprocessor(CPUState *cpu,\n gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,\n- const GDBFeature *feature, int g_pos);\n+ const GDBFeature *feature);\n \n /**\n * gdb_unregister_coprocessor_all() - unregisters supplemental set of registers\ndiff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c\nindex 6eadae3804e..882bc67e182 100644\n--- a/gdbstub/gdbstub.c\n+++ b/gdbstub/gdbstub.c\n@@ -604,13 +604,14 @@ void gdb_init_cpu(CPUState *cpu)\n \n void gdb_register_coprocessor(CPUState *cpu,\n gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg,\n- const GDBFeature *feature, int g_pos)\n+ const GDBFeature *feature)\n {\n GDBRegisterState *s;\n guint i;\n- int base_reg = cpu->gdb_num_regs;\n+ int base_reg;\n \n- assert(!g_pos || g_pos == feature->base_reg);\n+ assert(feature->base_reg >= cpu->gdb_num_regs);\n+ base_reg = feature->base_reg;\n \n for (i = 0; i < cpu->gdb_regs->len; i++) {\n /* Check for duplicates. */\n@@ -624,14 +625,7 @@ void gdb_register_coprocessor(CPUState *cpu,\n \n /* Add to end of list. */\n cpu->gdb_num_regs += feature->num_regs;\n- if (g_pos) {\n- if (g_pos != base_reg) {\n- error_report(\"Error: Bad gdb register numbering for '%s', \"\n- \"expected %d got %d\", feature->xml, g_pos, base_reg);\n- } else {\n- cpu->gdb_num_g_regs = cpu->gdb_num_regs;\n- }\n- }\n+ cpu->gdb_num_g_regs = cpu->gdb_num_regs;\n }\n \n void gdb_unregister_coprocessor_all(CPUState *cpu)\ndiff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c\nindex c7d59fd3726..d6e29c4cf46 100644\n--- a/target/arm/gdbstub.c\n+++ b/target/arm/gdbstub.c\n@@ -534,15 +534,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)\n } else {\n if (arm_feature(env, ARM_FEATURE_NEON)) {\n gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,\n- gdb_find_static_feature(\"arm-neon.xml\"),\n- 0);\n+ gdb_find_static_feature(\"arm-neon.xml\"));\n } else if (cpu_isar_feature(aa32_simd_r32, cpu)) {\n gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,\n- gdb_find_static_feature(\"arm-vfp3.xml\"),\n- 0);\n+ gdb_find_static_feature(\"arm-vfp3.xml\"));\n } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) {\n gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,\n- gdb_find_static_feature(\"arm-vfp.xml\"), 0);\n+ gdb_find_static_feature(\"arm-vfp.xml\"));\n }\n if (!arm_feature(env, ARM_FEATURE_M)) {\n /*\n@@ -550,29 +548,26 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)\n * expose to gdb.\n */\n gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_sysreg,\n- gdb_find_static_feature(\"arm-vfp-sysregs.xml\"),\n- 0);\n+ gdb_find_static_feature(\"arm-vfp-sysregs.xml\"));\n }\n }\n if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) {\n gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,\n- gdb_find_static_feature(\"arm-m-profile-mve.xml\"),\n- 0);\n+ gdb_find_static_feature(\"arm-m-profile-mve.xml\"));\n }\n gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,\n- arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs),\n- 0);\n+ arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs));\n \n #ifdef CONFIG_TCG\n if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {\n gdb_register_coprocessor(cs,\n arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,\n- arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs), 0);\n+ arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs));\n #ifndef CONFIG_USER_ONLY\n if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n gdb_register_coprocessor(cs,\n arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,\n- arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs), 0);\n+ arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs));\n }\n #endif\n }\ndiff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c\nindex b71666c3a1d..a4fa740caf6 100644\n--- a/target/arm/gdbstub64.c\n+++ b/target/arm/gdbstub64.c\n@@ -887,24 +887,22 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU *cpu)\n isar_feature_aa64_sme(&cpu->isar)) {\n GDBFeature *feature = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs);\n gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,\n- aarch64_gdb_set_sve_reg, feature, 0);\n+ aarch64_gdb_set_sve_reg, feature);\n } else {\n gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,\n aarch64_gdb_set_fpu_reg,\n- gdb_find_static_feature(\"aarch64-fpu.xml\"),\n- 0);\n+ gdb_find_static_feature(\"aarch64-fpu.xml\"));\n }\n \n if (isar_feature_aa64_sme(&cpu->isar)) {\n GDBFeature *sme_feature =\n arm_gen_dynamic_smereg_feature(cs, cs->gdb_num_regs);\n gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg,\n- aarch64_gdb_set_sme_reg, sme_feature, 0);\n+ aarch64_gdb_set_sme_reg, sme_feature);\n if (isar_feature_aa64_sme2(&cpu->isar)) {\n gdb_register_coprocessor(cs, aarch64_gdb_get_sme2_reg,\n aarch64_gdb_set_sme2_reg,\n- gdb_find_static_feature(\"aarch64-sme2.xml\"),\n- 0);\n+ gdb_find_static_feature(\"aarch64-sme2.xml\"));\n }\n }\n /*\n@@ -916,8 +914,7 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU *cpu)\n if (isar_feature_aa64_pauth(&cpu->isar)) {\n gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,\n aarch64_gdb_set_pauth_reg,\n- gdb_find_static_feature(\"aarch64-pauth.xml\"),\n- 0);\n+ gdb_find_static_feature(\"aarch64-pauth.xml\"));\n }\n \n #ifdef CONFIG_USER_ONLY\n@@ -925,14 +922,12 @@ void aarch64_cpu_register_gdb_regs_for_features(ARMCPU *cpu)\n if (cpu_isar_feature(aa64_mte, cpu)) {\n gdb_register_coprocessor(cs, aarch64_gdb_get_tag_ctl_reg,\n aarch64_gdb_set_tag_ctl_reg,\n- gdb_find_static_feature(\"aarch64-mte.xml\"),\n- 0);\n+ gdb_find_static_feature(\"aarch64-mte.xml\"));\n }\n #endif\n \n /* All AArch64 CPUs have at least TPIDR */\n gdb_register_coprocessor(cs, aarch64_gdb_get_tls_reg,\n aarch64_gdb_set_tls_reg,\n- arm_gen_dynamic_tls_feature(cs, cs->gdb_num_regs),\n- 0);\n+ arm_gen_dynamic_tls_feature(cs, cs->gdb_num_regs));\n }\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 58a22ee41f2..ffd14bb4678 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -322,7 +322,7 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)\n \n gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register,\n hexagon_hvx_gdb_write_register,\n- gdb_find_static_feature(\"hexagon-hvx.xml\"), 0);\n+ gdb_find_static_feature(\"hexagon-hvx.xml\"));\n \n qemu_init_vcpu(cs);\n cpu_reset(cs);\ndiff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c\nindex f1ce90a046e..4e87b67cc13 100644\n--- a/target/i386/gdbstub.c\n+++ b/target/i386/gdbstub.c\n@@ -503,8 +503,7 @@ void x86_cpu_gdb_init(CPUState *cs)\n if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APXF) {\n gdb_register_coprocessor(cs, i386_cpu_gdb_get_egprs,\n i386_cpu_gdb_set_egprs,\n- gdb_find_static_feature(\"i386-64bit-apx.xml\"),\n- 0);\n+ gdb_find_static_feature(\"i386-64bit-apx.xml\"));\n }\n #endif\n \n@@ -512,10 +511,9 @@ void x86_cpu_gdb_init(CPUState *cs)\n gdb_register_coprocessor(cs, x86_cpu_gdb_read_linux_register,\n x86_cpu_gdb_write_linux_register,\n #ifdef TARGET_X86_64\n- gdb_find_static_feature(\"i386-64bit-linux.xml\"),\n+ gdb_find_static_feature(\"i386-64bit-linux.xml\"));\n #else\n- gdb_find_static_feature(\"i386-32bit-linux.xml\"),\n+ gdb_find_static_feature(\"i386-32bit-linux.xml\"));\n #endif\n- 0);\n #endif\n }\ndiff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c\nindex 23a5eecc20b..3e9bdfa8bbf 100644\n--- a/target/loongarch/gdbstub.c\n+++ b/target/loongarch/gdbstub.c\n@@ -180,16 +180,16 @@ void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)\n \n if (FIELD_EX32(env->cpucfg[2], CPUCFG2, FP)) {\n gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,\n- gdb_find_static_feature(\"loongarch-fpu.xml\"), 0);\n+ gdb_find_static_feature(\"loongarch-fpu.xml\"));\n }\n \n if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LSX)) {\n gdb_register_coprocessor(cs, loongarch_gdb_get_lsx, loongarch_gdb_set_lsx,\n- gdb_find_static_feature(\"loongarch-lsx.xml\"), 0);\n+ gdb_find_static_feature(\"loongarch-lsx.xml\"));\n }\n \n if (FIELD_EX32(env->cpucfg[2], CPUCFG2, LASX)) {\n gdb_register_coprocessor(cs, loongarch_gdb_get_lasx, loongarch_gdb_set_lasx,\n- gdb_find_static_feature(\"loongarch-lasx.xml\"), 0);\n+ gdb_find_static_feature(\"loongarch-lasx.xml\"));\n }\n }\ndiff --git a/target/m68k/helper.c b/target/m68k/helper.c\nindex c566cb0a16c..9bab1843892 100644\n--- a/target/m68k/helper.c\n+++ b/target/m68k/helper.c\n@@ -129,10 +129,10 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)\n \n if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {\n gdb_register_coprocessor(cs, cf_fpu_gdb_get_reg, cf_fpu_gdb_set_reg,\n- gdb_find_static_feature(\"cf-fp.xml\"), 0);\n+ gdb_find_static_feature(\"cf-fp.xml\"));\n } else if (m68k_feature(env, M68K_FEATURE_FPU)) {\n gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, m68k_fpu_gdb_set_reg,\n- gdb_find_static_feature(\"m68k-fp.xml\"), 0);\n+ gdb_find_static_feature(\"m68k-fp.xml\"));\n }\n /* TODO: Add [E]MAC registers. */\n }\ndiff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c\nindex ae41a1a3287..ec513ae82d4 100644\n--- a/target/microblaze/cpu.c\n+++ b/target/microblaze/cpu.c\n@@ -265,8 +265,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)\n \n gdb_register_coprocessor(cs, mb_cpu_gdb_read_stack_protect,\n mb_cpu_gdb_write_stack_protect,\n- gdb_find_static_feature(\"microblaze-stack-protect.xml\"),\n- 0);\n+ gdb_find_static_feature(\"microblaze-stack-protect.xml\"));\n \n qemu_init_vcpu(cs);\n \ndiff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c\nindex e0aae9c9eaf..4d622c5cad5 100644\n--- a/target/ppc/gdbstub.c\n+++ b/target/ppc/gdbstub.c\n@@ -502,24 +502,23 @@ void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc)\n {\n if (pcc->insns_flags & PPC_FLOAT) {\n gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,\n- gdb_find_static_feature(\"power-fpu.xml\"), 0);\n+ gdb_find_static_feature(\"power-fpu.xml\"));\n }\n if (pcc->insns_flags & PPC_ALTIVEC) {\n gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,\n- gdb_find_static_feature(\"power-altivec.xml\"),\n- 0);\n+ gdb_find_static_feature(\"power-altivec.xml\"));\n }\n if (pcc->insns_flags & PPC_SPE) {\n gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,\n- gdb_find_static_feature(\"power-spe.xml\"), 0);\n+ gdb_find_static_feature(\"power-spe.xml\"));\n }\n if (pcc->insns_flags2 & PPC2_VSX) {\n gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg,\n- gdb_find_static_feature(\"power-vsx.xml\"), 0);\n+ gdb_find_static_feature(\"power-vsx.xml\"));\n }\n #ifndef CONFIG_USER_ONLY\n gdb_gen_spr_feature(cs);\n gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg,\n- &pcc->gdb_spr, 0);\n+ &pcc->gdb_spr);\n #endif\n }\ndiff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c\nindex a053009ccd3..6a5b7a82fd4 100644\n--- a/target/riscv/gdbstub.c\n+++ b/target/riscv/gdbstub.c\n@@ -348,32 +348,27 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)\n CPURISCVState *env = &cpu->env;\n if (env->misa_ext & RVD) {\n gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,\n- gdb_find_static_feature(\"riscv-64bit-fpu.xml\"),\n- 0);\n+ gdb_find_static_feature(\"riscv-64bit-fpu.xml\"));\n } else if (env->misa_ext & RVF) {\n gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,\n- gdb_find_static_feature(\"riscv-32bit-fpu.xml\"),\n- 0);\n+ gdb_find_static_feature(\"riscv-32bit-fpu.xml\"));\n }\n if (cpu->cfg.ext_zve32x) {\n gdb_register_coprocessor(cs, riscv_gdb_get_vector,\n riscv_gdb_set_vector,\n- ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),\n- 0);\n+ ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs));\n }\n switch (mcc->def->misa_mxl_max) {\n case MXL_RV32:\n gdb_register_coprocessor(cs, riscv_gdb_get_virtual,\n riscv_gdb_set_virtual,\n- gdb_find_static_feature(\"riscv-32bit-virtual.xml\"),\n- 0);\n+ gdb_find_static_feature(\"riscv-32bit-virtual.xml\"));\n break;\n case MXL_RV64:\n case MXL_RV128:\n gdb_register_coprocessor(cs, riscv_gdb_get_virtual,\n riscv_gdb_set_virtual,\n- gdb_find_static_feature(\"riscv-64bit-virtual.xml\"),\n- 0);\n+ gdb_find_static_feature(\"riscv-64bit-virtual.xml\"));\n break;\n default:\n g_assert_not_reached();\n@@ -381,7 +376,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)\n \n if (cpu->cfg.ext_zicsr) {\n gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,\n- riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs),\n- 0);\n+ riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs));\n }\n }\ndiff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c\nindex 9ae715add4d..efdaaefa6d0 100644\n--- a/target/s390x/gdbstub.c\n+++ b/target/s390x/gdbstub.c\n@@ -347,34 +347,33 @@ void s390_cpu_gdb_init(CPUState *cs)\n {\n gdb_register_coprocessor(cs, cpu_read_ac_reg,\n cpu_write_ac_reg,\n- gdb_find_static_feature(\"s390-acr.xml\"), 0);\n+ gdb_find_static_feature(\"s390-acr.xml\"));\n \n gdb_register_coprocessor(cs, cpu_read_fp_reg,\n cpu_write_fp_reg,\n- gdb_find_static_feature(\"s390-fpr.xml\"), 0);\n+ gdb_find_static_feature(\"s390-fpr.xml\"));\n \n gdb_register_coprocessor(cs, cpu_read_vreg,\n cpu_write_vreg,\n- gdb_find_static_feature(\"s390-vx.xml\"), 0);\n+ gdb_find_static_feature(\"s390-vx.xml\"));\n \n gdb_register_coprocessor(cs, cpu_read_gs_reg,\n cpu_write_gs_reg,\n- gdb_find_static_feature(\"s390-gs.xml\"), 0);\n+ gdb_find_static_feature(\"s390-gs.xml\"));\n \n #ifndef CONFIG_USER_ONLY\n gdb_register_coprocessor(cs, cpu_read_c_reg,\n cpu_write_c_reg,\n- gdb_find_static_feature(\"s390-cr.xml\"), 0);\n+ gdb_find_static_feature(\"s390-cr.xml\"));\n \n gdb_register_coprocessor(cs, cpu_read_virt_reg,\n cpu_write_virt_reg,\n- gdb_find_static_feature(\"s390-virt.xml\"), 0);\n+ gdb_find_static_feature(\"s390-virt.xml\"));\n \n if (kvm_enabled()) {\n gdb_register_coprocessor(cs, cpu_read_virt_kvm_reg,\n cpu_write_virt_kvm_reg,\n- gdb_find_static_feature(\"s390-virt-kvm.xml\"),\n- 0);\n+ gdb_find_static_feature(\"s390-virt-kvm.xml\"));\n }\n #endif\n }\ndiff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c\nindex 792bf70a145..2874ce1b350 100644\n--- a/target/sparc/gdbstub.c\n+++ b/target/sparc/gdbstub.c\n@@ -271,20 +271,16 @@ void sparc_cpu_register_gdb_regs(CPUState *cs)\n #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,\n sparc_fpu_gdb_write_register,\n- gdb_find_static_feature(\"sparc32-fpu.xml\"),\n- 0);\n+ gdb_find_static_feature(\"sparc32-fpu.xml\"));\n gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,\n sparc_cp0_gdb_write_register,\n- gdb_find_static_feature(\"sparc32-cp0.xml\"),\n- 0);\n+ gdb_find_static_feature(\"sparc32-cp0.xml\"));\n #else\n gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,\n sparc_fpu_gdb_write_register,\n- gdb_find_static_feature(\"sparc64-fpu.xml\"),\n- 0);\n+ gdb_find_static_feature(\"sparc64-fpu.xml\"));\n gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,\n sparc_cp0_gdb_write_register,\n- gdb_find_static_feature(\"sparc64-cp0.xml\"),\n- 0);\n+ gdb_find_static_feature(\"sparc64-cp0.xml\"));\n #endif\n }\n", "prefixes": [ "4/4" ] }