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GET /api/patches/2202595/?format=api
{ "id": 2202595, "url": "http://patchwork.ozlabs.org/api/patches/2202595/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203944.746471-5-chad@jablonski.xyz/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227203944.746471-5-chad@jablonski.xyz>", "list_archive_url": null, "date": "2026-02-27T20:39:30", "name": "[v9,04/18] ati-vga: Latch src and dst pitch and offset on master_cntl default", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b313413fee030483e1412b7c5151c52f72da358b", "submitter": { "id": 91805, "url": "http://patchwork.ozlabs.org/api/people/91805/?format=api", "name": "Chad Jablonski", "email": "chad@jablonski.xyz" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203944.746471-5-chad@jablonski.xyz/mbox/", "series": [ { "id": 493814, "url": "http://patchwork.ozlabs.org/api/series/493814/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493814", "date": "2026-02-27T20:39:27", "name": "ati-vga: Implement HOST_DATA transfers to enable X.org text rendering", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/493814/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2202595/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2202595/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=jablonski.xyz header.i=@jablonski.xyz\n header.a=rsa-sha256 header.s=fm2 header.b=cBQmNHlZ;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=messagingengine.com header.i=@messagingengine.com\n header.a=rsa-sha256 header.s=fm3 header.b=oaREIXSr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=\n messagingengine.com; h=cc:cc:content-transfer-encoding\n :content-type:date:date:feedback-id:feedback-id:from:from\n :in-reply-to:in-reply-to:message-id:mime-version:references\n :reply-to:subject:subject:to:to:x-me-proxy:x-me-sender\n :x-me-sender:x-sasl-enc; s=fm3; t=1772224859; x=1772311259; bh=i\n ZFopa7BN2v/Wniu8RWnxAcgO5JG4vm8jdapubVGmHM=; b=oaREIXSrRvE38Aihh\n DXxE27dHeHP0AmS72fw6v0/ExAERHWqDF/yJqNT+26R6oxChBCxt/QpdaTwRFVEo\n gO/sYbrmHUUt1ow6lL5kn2cDVStKsV4mHnT8OcgIbC0PYF/h5Xu6xeEmFjwg6T3C\n ZeLPt4b+pttp6m4ve6D4IDydNUTyTaM9s41ghos9Vu8GmBhC+tJk5FSNOy//lnab\n peEihGz0pYCBJ2DQynikHcWD5Vpc0BdjqFGPUjiqvPM3si27B3zqX6WSF2dV6Jfq\n wecuIcsgiWBIs2jC9HsbkOn8RQiNGmelZUc7w/o/Q1q/JgcEg9Qr7Rum8ATENB1B\n n91cQ==" ], "X-ME-Sender": "<xms:WwGiaYAhIThSBtIieFkfP-aObntsRhl19CbQn7uVZEBO5FcL_Ri63w>\n <xme:WwGiaRYqYafqJwx1__0GNCXqh6jCE92NcXczmqqBb78rS3s8JoYXVAk0RwqmSjgcR\n s7EGTV9BkR-EaMv1MoBzGtFV47AQUSdghwp3HeBLvmG8YUXLQuyAwI>", "X-ME-Received": "\n <xmr:WwGiaT5CiRNLuhebnnBeEac0szD9-DCof9iWmW_54RGH2tW3VLV6O0xmjphZ>", "X-ME-Proxy-Cause": "\n gggruggvucftvghtrhhoucdtuddrgeefgedrtddtgddvgeelleekucetufdoteggodetrf\n dotffvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfurfetoffkrfgpnffqhgenuceu\n rghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnegfrh\n hlucfvnfffucdljedtmdenucfjughrpefhvfevufffkffojghfggfgsedtkeertdertddt\n necuhfhrohhmpeevhhgrugculfgrsghlohhnshhkihcuoegthhgrugesjhgrsghlohhnsh\n hkihdrgiihiieqnecuggftrfgrthhtvghrnhepgfeiteejhfelheefieetjefgleejfffh\n ueffvdduieejgfeuueeuvddvkeejhfelnecuvehluhhsthgvrhfuihiivgepudenucfrrg\n hrrghmpehmrghilhhfrhhomheptghhrggusehjrggslhhonhhskhhirdighiiipdhnsggp\n rhgtphhtthhopeehpdhmohguvgepshhmthhpohhuthdprhgtphhtthhopegsrghlrghtoh\n hnsegvihhkrdgsmhgvrdhhuhdprhgtphhtthhopehmrghrtggrnhgurhgvrdhluhhrvggr\n uhesrhgvughhrghtrdgtohhmpdhrtghpthhtoheptghhrggusehjrggslhhonhhskhhird\n ighiiipdhrtghpthhtohepkhhrrgigvghlsehrvgguhhgrthdrtghomhdprhgtphhtthho\n pehqvghmuhdquggvvhgvlhesnhhonhhgnhhurdhorhhg", "X-ME-Proxy": "<xmx:WwGiaaYSvv0XBG3pE4y9GY5DMp9QyairfBeW2ml7dpk0QSHqXIS15A>\n <xmx:WwGiaajRzCifUunaU0wJvY91nevKDvxPSssTF-fcx6AleA-XVlmoYQ>\n <xmx:WwGiaT-Obl7D0qVZGHIQNyLqazi1odRD4PXHeBZ0SGZqVIRR9rilXg>\n <xmx:WwGiadpyLKO1E-6Hat8DE6N2vN7FvOeUO5L_6og3wtBDnvMAmauulQ>\n <xmx:WwGiac3YlEbqXoURx5iYgyWXGlr3fnLeFBGKU1L4uNYimNLY0MiXcl4v>", "Feedback-ID": "ib26944c1:Fastmail", "From": "Chad Jablonski <chad@jablonski.xyz>", "To": "qemu-devel@nongnu.org", "Cc": "BALATON Zoltan <balaton@eik.bme.hu>, Gerd Hoffmann <kraxel@redhat.com>,\n\t=?utf-8?q?Marc-Andr=C3=A9_Lureau?= <marcandre.lureau@redhat.com>,\n Chad Jablonski <chad@jablonski.xyz>", "Subject": "[PATCH v9 04/18] ati-vga: Latch src and dst pitch and offset on\n master_cntl default", "Date": "Fri, 27 Feb 2026 15:39:30 -0500", "Message-ID": "<20260227203944.746471-5-chad@jablonski.xyz>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20260227203944.746471-1-chad@jablonski.xyz>", "References": "<20260227203944.746471-1-chad@jablonski.xyz>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=103.168.172.144;\n envelope-from=chad@jablonski.xyz;\n helo=fout-a1-smtp.messagingengine.com", "X-Spam_score_int": "8", "X-Spam_score": "0.8", "X-Spam_bar": "/", "X-Spam_report": "(0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1,\n DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FROM_SUSPICIOUS_NTLD=0.5,\n PDS_OTHER_BAD_TLD=1.999, RCVD_IN_DNSWL_LOW=-0.7,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.706,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.401,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001,\n UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Hardware testing on the Rage 128 confirms that (SRC/DST)_OFFSET,\nand (SRC/DST)_PITCH are latched when (SRC/DST)_PITCH_OFFSET_CNTL bits\nin DP_GUI_MASTER_CNTL are set to \"default\".\n\nThe earlier approach looked at the state of the (SRC/DST)_PITCH_OFFSET_CNTL\nbits when offset and pitch registers were used. This meant that when\n(SRC/DST)_PITCH_OFFSET_CNTL was reset to \"leave alone\" the old values\nstored in the registers would return. This is not how the real hardware\nworks.\n\nSigned-off-by: Chad Jablonski <chad@jablonski.xyz>\nReviewed-by: BALATON Zoltan <balaton@eik.bme.hu>\n---\n hw/display/ati.c | 9 +++++++++\n hw/display/ati_2d.c | 13 ++++---------\n 2 files changed, 13 insertions(+), 9 deletions(-)", "diff": "diff --git a/hw/display/ati.c b/hw/display/ati.c\nindex 028efd13e1..ce23e5e48b 100644\n--- a/hw/display/ati.c\n+++ b/hw/display/ati.c\n@@ -868,6 +868,15 @@ static void ati_mm_write(void *opaque, hwaddr addr,\n s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 |\n (data & 0x4000) << 16;\n s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16;\n+\n+ if (!(data & GMC_SRC_PITCH_OFFSET_CNTL)) {\n+ s->regs.src_offset = s->regs.default_offset;\n+ s->regs.src_pitch = s->regs.default_pitch;\n+ }\n+ if (!(data & GMC_DST_PITCH_OFFSET_CNTL)) {\n+ s->regs.dst_offset = s->regs.default_offset;\n+ s->regs.dst_pitch = s->regs.default_pitch;\n+ }\n break;\n case DST_WIDTH_X:\n s->regs.dst_x = data & 0x3fff;\ndiff --git a/hw/display/ati_2d.c b/hw/display/ati_2d.c\nindex 309bb5ccb6..a8c4c534b9 100644\n--- a/hw/display/ati_2d.c\n+++ b/hw/display/ati_2d.c\n@@ -43,8 +43,6 @@ static int ati_bpp_from_datatype(ATIVGAState *s)\n }\n }\n \n-#define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)\n-\n void ati_2d_blt(ATIVGAState *s)\n {\n /* FIXME it is probably more complex than this and may need to be */\n@@ -63,13 +61,12 @@ void ati_2d_blt(ATIVGAState *s)\n qemu_log_mask(LOG_GUEST_ERROR, \"Invalid bpp\\n\");\n return;\n }\n- int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;\n+ int dst_stride = s->regs.dst_pitch;\n if (!dst_stride) {\n qemu_log_mask(LOG_GUEST_ERROR, \"Zero dest pitch\\n\");\n return;\n }\n- uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?\n- s->regs.dst_offset : s->regs.default_offset);\n+ uint8_t *dst_bits = s->vga.vram_ptr + s->regs.dst_offset;\n \n if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n dst_bits += s->regs.crtc_offset & 0x07ffffff;\n@@ -97,14 +94,12 @@ void ati_2d_blt(ATIVGAState *s)\n s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);\n unsigned src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?\n s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);\n- int src_stride = DEFAULT_CNTL ?\n- s->regs.src_pitch : s->regs.default_pitch;\n+ int src_stride = s->regs.src_pitch;\n if (!src_stride) {\n qemu_log_mask(LOG_GUEST_ERROR, \"Zero source pitch\\n\");\n return;\n }\n- uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?\n- s->regs.src_offset : s->regs.default_offset);\n+ uint8_t *src_bits = s->vga.vram_ptr + s->regs.src_offset;\n \n if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {\n src_bits += s->regs.crtc_offset & 0x07ffffff;\n", "prefixes": [ "v9", "04/18" ] }