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GET /api/patches/2202580/?format=api
{ "id": 2202580, "url": "http://patchwork.ozlabs.org/api/patches/2202580/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-18-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227203627.932864-18-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-27T20:36:07", "name": "[v3,17/37] target/hexagon: Add new macro definitions for sysemu", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1eb8c5dc709e9d44040d0f3be086ac1489df1d55", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-18-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 493813, "url": "http://patchwork.ozlabs.org/api/series/493813/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493813", "date": "2026-02-27T20:35:57", "name": "Hexagon system emulation - Part 1/3", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/493813/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2202580/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2202580/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=jJpNinZM;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=gps/voCS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-GUID": "f1IPRsIfp9kqJ1QuBOiXRAh96-P2ri1Z", "X-Authority-Analysis": "v=2.4 cv=PN8COPqC c=1 sm=1 tr=0 ts=69a20069 cx=c_pps\n a=z9lCQkyTxNhZyzAvolXo/A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22\n a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=VoFV4bgUeqxKQXHmsMYA:9 a=QEXdDO2ut3YA:10\n a=EyFUmsFV_t8cxB2kMr4A:22 a=TjNXssC_j7lpFel5tvFf:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjI3MDE4MSBTYWx0ZWRfX1at4PD4HtwU/\n SPtaZdm0ciu9uYFo+mPOc9SFQQDZvRgXLR2Ly3RhPlf0FkNoJPQgQwFk9eJXhJtauPQ3jZMXpa8\n kG8OaNzB5HnKd5OpE5hsmm1+p8+85QBzBoR2L2B3uDssIH9Glu+0UrFzwWw9BWvJvdh+PI2+GMr\n ZH7kU8sfbzy+F04DbPdjwilZylNVcYYX1L0ER4vSmtZXJSpPQRImDXGjOWGzRs/OUfHxNMw+ozt\n l6mFgyxMC7TeRRQDc+tArmG0FkArUHaH0qDV4HwZIIA3NGyOp0YJbQ/ILWr2Vhx6Z/gANl83qfT\n oiRxYx98svD7P80XXwYEvHvpKojU2Ox7vkR0B/evDlGyRHg/0ySetzJswbPEl72s10qDu4abzVn\n Uxcur3hl2XFN6j7x/TA09YN+utckvR7fN48hppTfqBoDrKMdU+c3ZAMG2v6gdk3GVjS3lS7fRq2\n u78P7ojka/fgjmQwKjQ==", "X-Proofpoint-ORIG-GUID": "f1IPRsIfp9kqJ1QuBOiXRAh96-P2ri1Z", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-27_04,2026-02-27_03,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 impostorscore=0 clxscore=1015 lowpriorityscore=0\n adultscore=0 spamscore=0 phishscore=0 suspectscore=0 bulkscore=0\n malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000\n definitions=main-2602270181", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.706,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.401, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nAlso: add nop TCG overrides for break, unpause, fetchbo; add TCG\noverride for dczeroa_nt (non-temporal variant of dczeroa).\n\nbreak: this hardware breakpoint instruction is used with the in-silicon\ndebugger feature, this is not modeled.\n\nunpause: this instruction is used to resume hardware threads that are\nstalled by pause instructions. pause is modeled as a nop, or in RR\nmode as an EXCP_YIELD. This instruction is safe to ignore.\n\nSince prefetch functions are not modeled, fetchbo is safe to ignore.\n\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu_bits.h | 7 ++\n target/hexagon/gen_tcg.h | 9 ++\n target/hexagon/macros.h | 25 +++-\n target/hexagon/sys_macros.h | 237 ++++++++++++++++++++++++++++++++++++\n target/hexagon/op_helper.c | 1 +\n 5 files changed, 278 insertions(+), 1 deletion(-)\n create mode 100644 target/hexagon/sys_macros.h", "diff": "diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h\nindex 91e9da09e03..3cbf8b7f570 100644\n--- a/target/hexagon/cpu_bits.h\n+++ b/target/hexagon/cpu_bits.h\n@@ -97,6 +97,13 @@ enum hex_cause {\n HEX_CAUSE_INT7 = 0x0c7,\n };\n \n+enum data_cache_state {\n+ HEX_DC_STATE_INVALID = 0x0,\n+ HEX_DC_STATE_VALID = 0x1,\n+ HEX_DC_STATE_RESERVED = 0x2,\n+ HEX_DC_STATE_UNUSED_WT = 0x3,\n+};\n+\n #define PACKET_WORDS_MAX 4\n \n static inline uint32_t parse_bits(uint32_t encoding)\ndiff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h\nindex 7b96dab9185..bd04386d860 100644\n--- a/target/hexagon/gen_tcg.h\n+++ b/target/hexagon/gen_tcg.h\n@@ -488,6 +488,7 @@\n \n /* dczeroa clears the 32 byte cache line at the address given */\n #define fGEN_TCG_Y2_dczeroa(SHORTCODE) SHORTCODE\n+#define fGEN_TCG_Y2_dczeroa_nt(SHORTCODE) SHORTCODE\n \n /* In linux-user mode, these are not modelled, suppress compiler warning */\n #define fGEN_TCG_Y2_dcinva(SHORTCODE) \\\n@@ -1132,6 +1133,9 @@\n RdV, tcg_constant_tl(0)); \\\n } while (0)\n \n+#define fGEN_TCG_Y2_break(SHORTCODE)\n+#define fGEN_TCG_J2_unpause(SHORTCODE)\n+\n #define fGEN_TCG_J2_pause(SHORTCODE) \\\n do { \\\n uiV = uiV; \\\n@@ -1341,6 +1345,11 @@\n RsV = RsV; \\\n uiV = uiV; \\\n } while (0)\n+#define fGEN_TCG_Y2_dcfetchbo_nt(SHORTCODE) \\\n+ do { \\\n+ RsV = RsV; \\\n+ uiV = uiV; \\\n+ } while (0)\n \n #define fGEN_TCG_L2_loadw_aq(SHORTCODE) SHORTCODE\n #define fGEN_TCG_L4_loadd_aq(SHORTCODE) SHORTCODE\ndiff --git a/target/hexagon/macros.h b/target/hexagon/macros.h\nindex 6c2862a2320..e4bfea4923f 100644\n--- a/target/hexagon/macros.h\n+++ b/target/hexagon/macros.h\n@@ -631,8 +631,18 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)\n #define fCONSTLL(A) A##LL\n #define fECHO(A) (A)\n \n-#define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)\n+#ifdef CONFIG_USER_ONLY\n+#define fTRAP(TRAPTYPE, IMM) \\\n+ do { \\\n+ hexagon_raise_exception_err(env, HEX_EVENT_TRAP0, PC); \\\n+ } while (0)\n+#endif\n+\n+#define fDO_TRACE(SREG)\n+#define fBREAK()\n+#define fUNPAUSE()\n #define fPAUSE(IMM)\n+#define fDCFETCH(REG)\n \n #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \\\n ((VAL) << reg_field_info[FIELD].offset)\n@@ -654,5 +664,18 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)\n #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \\\n STRBITNUM) /* Nothing */\n \n+#ifdef CONFIG_USER_ONLY\n+/*\n+ * This macro can only be true in guest mode.\n+ * In user mode, the 4 VIRTINSN's can't be reached\n+ */\n+#define fTRAP1_VIRTINSN(IMM) (false)\n+#define fVIRTINSN_SPSWAP(IMM, REG) g_assert_not_reached()\n+#define fVIRTINSN_GETIE(IMM, REG) g_assert_not_reached()\n+#define fVIRTINSN_SETIE(IMM, REG) g_assert_not_reached()\n+#define fVIRTINSN_RTE(IMM, REG) g_assert_not_reached()\n+#endif\n+\n+#define fPREDUSE_TIMING()\n \n #endif\ndiff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h\nnew file mode 100644\nindex 00000000000..3b66b83695c\n--- /dev/null\n+++ b/target/hexagon/sys_macros.h\n@@ -0,0 +1,237 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HEXAGON_SYS_MACROS_H\n+#define HEXAGON_SYS_MACROS_H\n+\n+/*\n+ * Macro definitions for Hexagon system mode\n+ */\n+\n+#ifndef CONFIG_USER_ONLY\n+\n+#define READ_SGP0() (env->t_sreg[HEX_SREG_SGP0])\n+#define READ_SGP1() (env->t_sreg[HEX_SREG_SGP1])\n+#define READ_SGP10() ((uint64_t)(env->t_sreg[HEX_SREG_SGP0]) | \\\n+ ((uint64_t)(env->t_sreg[HEX_SREG_SGP1]) << 32))\n+\n+#define WRITE_SGP0(VAL) log_sreg_write(env, HEX_SREG_SGP0, VAL, slot)\n+#define WRITE_SGP1(VAL) log_sreg_write(env, HEX_SREG_SGP1, VAL, slot)\n+#define WRITE_SGP10(VAL) \\\n+ do { \\\n+ log_sreg_write(env, HEX_SREG_SGP0, (VAL) & 0xFFFFFFFF, slot); \\\n+ log_sreg_write(env, HEX_SREG_SGP1, (VAL) >> 32, slot); \\\n+ } while (0)\n+\n+#ifdef QEMU_GENERATE\n+#define GET_SSR_FIELD(RES, FIELD) \\\n+ GET_FIELD(RES, FIELD, hex_t_sreg[HEX_SREG_SSR])\n+#else\n+\n+#define GET_SSR_FIELD(FIELD, REGIN) \\\n+ (uint32_t)GET_FIELD(FIELD, REGIN)\n+#define GET_SYSCFG_FIELD(FIELD, REGIN) \\\n+ (uint32_t)GET_FIELD(FIELD, REGIN)\n+#define SET_SYSTEM_FIELD(ENV, REG, FIELD, VAL) \\\n+ do { \\\n+ uint32_t regval = arch_get_system_reg(ENV, REG); \\\n+ fINSERT_BITS(regval, reg_field_info[FIELD].width, \\\n+ reg_field_info[FIELD].offset, (VAL)); \\\n+ arch_set_system_reg(ENV, REG, regval); \\\n+ } while (0)\n+#define SET_SSR_FIELD(ENV, FIELD, VAL) \\\n+ SET_SYSTEM_FIELD(ENV, HEX_SREG_SSR, FIELD, VAL)\n+#define SET_SYSCFG_FIELD(ENV, FIELD, VAL) \\\n+ SET_SYSTEM_FIELD(ENV, HEX_SREG_SYSCFG, FIELD, VAL)\n+\n+#define CCR_FIELD_SET(ENV, FIELD) \\\n+ (!!GET_FIELD(FIELD, (ENV)->t_sreg[HEX_SREG_CCR]))\n+\n+/*\n+ * Direct-to-guest is not implemented yet, continuing would cause unexpected\n+ * behavior, so we abort.\n+ */\n+#define ASSERT_DIRECT_TO_GUEST_UNSET(ENV, EXCP) \\\n+ do { \\\n+ switch (EXCP) { \\\n+ case HEX_EVENT_TRAP0: \\\n+ g_assert(!CCR_FIELD_SET(ENV, CCR_GTE)); \\\n+ break; \\\n+ case HEX_EVENT_IMPRECISE: \\\n+ case HEX_EVENT_PRECISE: \\\n+ case HEX_EVENT_FPTRAP: \\\n+ g_assert(!CCR_FIELD_SET(ENV, CCR_GEE)); \\\n+ break; \\\n+ default: \\\n+ if ((EXCP) >= HEX_EVENT_INT0) { \\\n+ g_assert(!CCR_FIELD_SET(ENV, CCR_GIE)); \\\n+ } \\\n+ break; \\\n+ } \\\n+ } while (0)\n+#endif\n+\n+#define fREAD_ELR() (env->t_sreg[HEX_SREG_ELR])\n+\n+#define fLOAD_PHYS(NUM, SIZE, SIGN, SRC1, SRC2, DST) { \\\n+ const uintptr_t rs = ((unsigned long)(unsigned)(SRC1)) & 0x7ff; \\\n+ const uintptr_t rt = ((unsigned long)(unsigned)(SRC2)) << 11; \\\n+ const uintptr_t addr = rs + rt; \\\n+ cpu_physical_memory_read(addr, &DST, sizeof(uint32_t)); \\\n+}\n+\n+#define fPOW2_HELP_ROUNDUP(VAL) \\\n+ ((VAL) | \\\n+ ((VAL) >> 1) | \\\n+ ((VAL) >> 2) | \\\n+ ((VAL) >> 4) | \\\n+ ((VAL) >> 8) | \\\n+ ((VAL) >> 16))\n+#define fPOW2_ROUNDUP(VAL) (fPOW2_HELP_ROUNDUP((VAL) - 1) + 1)\n+\n+#define fTRAP(TRAPTYPE, IMM) \\\n+ register_trap_exception(env, TRAPTYPE, IMM, PC)\n+\n+#define fVIRTINSN_SPSWAP(IMM, REG)\n+#define fVIRTINSN_GETIE(IMM, REG) { REG = 0xdeafbeef; }\n+#define fVIRTINSN_SETIE(IMM, REG)\n+#define fVIRTINSN_RTE(IMM, REG)\n+#define fGRE_ENABLED() \\\n+ GET_FIELD(CCR_GRE, env->t_sreg[HEX_SREG_CCR])\n+#define fTRAP1_VIRTINSN(IMM) \\\n+ (fGRE_ENABLED() && \\\n+ (((IMM) == 1) || ((IMM) == 3) || ((IMM) == 4) || ((IMM) == 6)))\n+\n+/* Not modeled in qemu */\n+\n+#define MARK_LATE_PRED_WRITE(RNUM)\n+#define fICINVIDX(REG)\n+#define fICKILL()\n+#define fDCKILL()\n+#define fL2KILL()\n+#define fL2UNLOCK()\n+#define fL2CLEAN()\n+#define fL2CLEANINV()\n+#define fL2CLEANPA(REG)\n+#define fL2CLEANINVPA(REG)\n+#define fL2CLEANINVIDX(REG)\n+#define fL2CLEANIDX(REG)\n+#define fL2INVIDX(REG)\n+#define fL2TAGR(INDEX, DST, DSTREG)\n+#define fL2UNLOCKA(VA) ((void) VA)\n+#define fL2TAGW(INDEX, PART2)\n+#define fDCCLEANIDX(REG)\n+#define fDCCLEANINVIDX(REG)\n+\n+/* Always succeed: */\n+#define fL2LOCKA(EA, PDV, PDN) ((void) EA, PDV = 0xFF)\n+#define fCLEAR_RTE_EX() \\\n+ do { \\\n+ uint32_t tmp = env->t_sreg[HEX_SREG_SSR]; \\\n+ fINSERT_BITS(tmp, reg_field_info[SSR_EX].width, \\\n+ reg_field_info[SSR_EX].offset, 0); \\\n+ log_sreg_write(env, HEX_SREG_SSR, tmp, slot); \\\n+ } while (0)\n+\n+#define fDCINVIDX(REG)\n+#define fDCINVA(REG) do { REG = REG; } while (0) /* Nothing to do in qemu */\n+\n+#define fSET_TLB_LOCK() g_assert_not_reached()\n+#define fCLEAR_TLB_LOCK() g_assert_not_reached()\n+\n+#define fSET_K0_LOCK() g_assert_not_reached()\n+#define fCLEAR_K0_LOCK() g_assert_not_reached()\n+\n+#define fTLB_IDXMASK(INDEX) \\\n+ ((INDEX) & (fPOW2_ROUNDUP( \\\n+ fCAST4u(hexagon_tlb_get_num_entries(env_archcpu(env)->tlb))) - 1))\n+\n+#define fTLB_NONPOW2WRAP(INDEX) \\\n+ (((INDEX) >= hexagon_tlb_get_num_entries(env_archcpu(env)->tlb)) ? \\\n+ ((INDEX) - hexagon_tlb_get_num_entries(env_archcpu(env)->tlb)) : \\\n+ (INDEX))\n+\n+\n+#define fTLBW(INDEX, VALUE) \\\n+ hex_tlbw(env, (INDEX), (VALUE))\n+#define fTLBW_EXTENDED(INDEX, VALUE) \\\n+ hex_tlbw(env, (INDEX), (VALUE))\n+#define fTLB_ENTRY_OVERLAP(VALUE) \\\n+ (hex_tlb_check_overlap(env, VALUE, -1) != -2)\n+#define fTLB_ENTRY_OVERLAP_IDX(VALUE) \\\n+ hex_tlb_check_overlap(env, VALUE, -1)\n+#define fTLBR(INDEX) \\\n+ hexagon_tlb_read(env_archcpu(env)->tlb, \\\n+ fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX)))\n+#define fTLBR_EXTENDED(INDEX) \\\n+ hexagon_tlb_read(env_archcpu(env)->tlb, \\\n+ fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX)))\n+#define fTLBP(TLBHI) \\\n+ hex_tlb_lookup(env, ((TLBHI) >> 12), ((TLBHI) << 12))\n+#define iic_flush_cache(p)\n+\n+#define fIN_DEBUG_MODE(TNUM) \\\n+ ((GET_FIELD(ISDBST_DEBUGMODE, arch_get_system_reg(env, HEX_SREG_ISDBST)) \\\n+ & (0x1 << (TNUM))) != 0)\n+\n+#define fIN_DEBUG_MODE_NO_ISDB(TNUM) false\n+#define fIN_DEBUG_MODE_WARN(TNUM) false\n+\n+#ifdef QEMU_GENERATE\n+\n+/*\n+ * Read tags back as zero for now:\n+ *\n+ * tag value in RD[31:10] for 32k, RD[31:9] for 16k\n+ */\n+#define fICTAGR(RS, RD, RD2) \\\n+ do { \\\n+ RD = ctx->zero; \\\n+ } while (0)\n+#define fICTAGW(RS, RD)\n+#define fICDATAR(RS, RD) \\\n+ do { \\\n+ RD = ctx->zero; \\\n+ } while (0)\n+#define fICDATAW(RS, RD)\n+\n+#define fDCTAGW(RS, RT)\n+/* tag: RD[23:0], state: RD[30:29] */\n+#define fDCTAGR(INDEX, DST, DST_REG_NUM) \\\n+ do { \\\n+ DST = ctx->zero; \\\n+ } while (0)\n+#else\n+\n+/*\n+ * Read tags back as zero for now:\n+ *\n+ * tag value in RD[31:10] for 32k, RD[31:9] for 16k\n+ */\n+#define fICTAGR(RS, RD, RD2) \\\n+ do { \\\n+ RD = 0x00; \\\n+ } while (0)\n+#define fICTAGW(RS, RD)\n+#define fICDATAR(RS, RD) \\\n+ do { \\\n+ RD = 0x00; \\\n+ } while (0)\n+#define fICDATAW(RS, RD)\n+\n+#define fDCTAGW(RS, RT)\n+/* tag: RD[23:0], state: RD[30:29] */\n+#define fDCTAGR(INDEX, DST, DST_REG_NUM) \\\n+ do { \\\n+ DST = HEX_DC_STATE_INVALID | 0x00; \\\n+ } while (0)\n+#endif\n+\n+#endif\n+\n+#define NUM_TLB_REGS(x) (hexagon_tlb_get_num_entries(env_archcpu(env)->tlb))\n+\n+#endif\ndiff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c\nindex 368391bb846..39f0c0445d6 100644\n--- a/target/hexagon/op_helper.c\n+++ b/target/hexagon/op_helper.c\n@@ -24,6 +24,7 @@\n #include \"cpu.h\"\n #include \"internal.h\"\n #include \"macros.h\"\n+#include \"sys_macros.h\"\n #include \"arch.h\"\n #include \"hex_arch_types.h\"\n #include \"fma_emu.h\"\n", "prefixes": [ "v3", "17/37" ] }