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GET /api/patches/2202569/?format=api
{ "id": 2202569, "url": "http://patchwork.ozlabs.org/api/patches/2202569/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-17-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227203627.932864-17-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-27T20:36:06", "name": "[v3,16/37] target/hexagon: Add imported macro, attr defs for sysemu", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a0caf84e5fc1ef51d3a8efdb3d881a5e70733594", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-17-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 493813, "url": "http://patchwork.ozlabs.org/api/series/493813/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493813", "date": "2026-02-27T20:35:57", "name": "Hexagon system emulation - Part 1/3", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/493813/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2202569/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2202569/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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anjo@rev.ng, Brian Cain <bcain@quicinc.com>", "Subject": "[PATCH v3 16/37] target/hexagon: Add imported macro,\n attr defs for sysemu", "Date": "Fri, 27 Feb 2026 12:36:06 -0800", "Message-Id": "<20260227203627.932864-17-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260227203627.932864-1-brian.cain@oss.qualcomm.com>", "References": "<20260227203627.932864-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Authority-Analysis": "v=2.4 cv=WZwBqkhX c=1 sm=1 tr=0 ts=69a20068 cx=c_pps\n a=lVi5GcDxkcJcfCmEjVJoaw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22\n a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=Qb_ubwlFxJMmFhvAiBAA:9 a=QEXdDO2ut3YA:10\n a=rBiNkAWo9uy_4UTK5NWh:22 a=TjNXssC_j7lpFel5tvFf:22", "X-Proofpoint-Spam-Details-Enc": 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clxscore=1015 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602270181", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.706,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.401, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/attribs_def.h.inc | 49 ++-\n target/hexagon/imported/macros.def | 558 +++++++++++++++++++++++++++++\n 2 files changed, 601 insertions(+), 6 deletions(-)\n mode change 100755 => 100644 target/hexagon/imported/macros.def", "diff": "diff --git a/target/hexagon/attribs_def.h.inc b/target/hexagon/attribs_def.h.inc\nindex 9e3a05f8828..06ab826b49f 100644\n--- a/target/hexagon/attribs_def.h.inc\n+++ b/target/hexagon/attribs_def.h.inc\n@@ -52,6 +52,9 @@ DEF_ATTRIB(REGWRSIZE_4B, \"Memory width is 4 bytes\", \"\", \"\")\n DEF_ATTRIB(REGWRSIZE_8B, \"Memory width is 8 bytes\", \"\", \"\")\n DEF_ATTRIB(MEMLIKE, \"Memory-like instruction\", \"\", \"\")\n DEF_ATTRIB(MEMLIKE_PACKET_RULES, \"follows Memory-like packet rules\", \"\", \"\")\n+DEF_ATTRIB(CACHEOP, \"Cache operation\", \"\", \"\")\n+DEF_ATTRIB(COPBYADDRESS, \"Cache operation by address\", \"\", \"\")\n+DEF_ATTRIB(COPBYIDX, \"Cache operation by index\", \"\", \"\")\n DEF_ATTRIB(RELEASE, \"Releases a lock\", \"\", \"\")\n DEF_ATTRIB(ACQUIRE, \"Acquires a lock\", \"\", \"\")\n \n@@ -101,23 +104,44 @@ DEF_ATTRIB(ROPS_3, \"Compound instruction worth 3 RISC-ops\", \"\", \"\")\n \n /* access to implicit registers */\n DEF_ATTRIB(IMPLICIT_WRITES_LR, \"Writes the link register\", \"\", \"UREG.LR\")\n+DEF_ATTRIB(IMPLICIT_READS_LR, \"Reads the link register\", \"UREG.LR\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_LC0, \"Reads loop count for loop 0\", \"UREG.LC0\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_LC1, \"Reads loop count for loop 1\", \"UREG.LC1\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_SA0, \"Reads start address for loop 0\", \"UREG.SA0\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_SA1, \"Reads start address for loop 1\", \"UREG.SA1\", \"\")\n+DEF_ATTRIB(IMPLICIT_WRITES_PC, \"Writes the program counter\", \"\", \"UREG.PC\")\n+DEF_ATTRIB(IMPLICIT_READS_PC, \"Reads the program counter\", \"UREG.PC\", \"\")\n DEF_ATTRIB(IMPLICIT_WRITES_SP, \"Writes the stack pointer\", \"\", \"UREG.SP\")\n+DEF_ATTRIB(IMPLICIT_READS_SP, \"Reads the stack pointer\", \"UREG.SP\", \"\")\n DEF_ATTRIB(IMPLICIT_WRITES_FP, \"Writes the frame pointer\", \"\", \"UREG.FP\")\n+DEF_ATTRIB(IMPLICIT_READS_FP, \"Reads the frame pointer\", \"UREG.FP\", \"\")\n+DEF_ATTRIB(IMPLICIT_WRITES_GP, \"Writes the GP register\", \"\", \"UREG.GP\")\n+DEF_ATTRIB(IMPLICIT_READS_GP, \"Reads the GP register\", \"UREG.GP\", \"\")\n DEF_ATTRIB(IMPLICIT_WRITES_LC0, \"Writes loop count for loop 0\", \"\", \"UREG.LC0\")\n DEF_ATTRIB(IMPLICIT_WRITES_LC1, \"Writes loop count for loop 1\", \"\", \"UREG.LC1\")\n DEF_ATTRIB(IMPLICIT_WRITES_SA0, \"Writes start addr for loop 0\", \"\", \"UREG.SA0\")\n DEF_ATTRIB(IMPLICIT_WRITES_SA1, \"Writes start addr for loop 1\", \"\", \"UREG.SA1\")\n+DEF_ATTRIB(IMPLICIT_WRITES_R00, \"Writes Register 0\", \"\", \"UREG.R00\")\n DEF_ATTRIB(IMPLICIT_WRITES_P0, \"Writes Predicate 0\", \"\", \"UREG.P0\")\n DEF_ATTRIB(IMPLICIT_WRITES_P1, \"Writes Predicate 1\", \"\", \"UREG.P1\")\n DEF_ATTRIB(IMPLICIT_WRITES_P2, \"Writes Predicate 1\", \"\", \"UREG.P2\")\n DEF_ATTRIB(IMPLICIT_WRITES_P3, \"May write Predicate 3\", \"\", \"UREG.P3\")\n-DEF_ATTRIB(IMPLICIT_READS_PC, \"Reads the PC register\", \"\", \"\")\n-DEF_ATTRIB(IMPLICIT_READS_P0, \"Reads the P0 register\", \"\", \"\")\n-DEF_ATTRIB(IMPLICIT_READS_P1, \"Reads the P1 register\", \"\", \"\")\n-DEF_ATTRIB(IMPLICIT_READS_P2, \"Reads the P2 register\", \"\", \"\")\n-DEF_ATTRIB(IMPLICIT_READS_P3, \"Reads the P3 register\", \"\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_R00, \"Reads Register 0\", \"UREG.R00\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_P0, \"Reads Predicate 0\", \"UREG.P0\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_P1, \"Reads Predicate 1\", \"UREG.P1\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_P3, \"Reads Predicate 3\", \"UREG.P3\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_Q3, \"Reads Vector Predicate 3\", \"UREG.Q3\", \"\")\n+DEF_ATTRIB(IMPLICIT_READS_CS, \"Reads the CS/M register\", \"UREG.CS\", \"\")\n DEF_ATTRIB(IMPLICIT_WRITES_USR, \"May write USR\", \"\", \"\")\n-DEF_ATTRIB(IMPLICIT_READS_SP, \"Reads the SP register\", \"\", \"\")\n+DEF_ATTRIB(IMPLICIT_WRITES_CCR, \"Writes CCR register\", \"\", \"UREG.CCR\")\n+DEF_ATTRIB(IMPLICIT_WRITES_GOSP, \"Writes GOSP register\", \"\", \"UREG.GOSP\")\n+DEF_ATTRIB(IMPLICIT_WRITES_SSR, \"Writes SSR register\", \"\", \"UREG.SSR\")\n+DEF_ATTRIB(IMPLICIT_WRITES_SGP0, \"Writes SGP0 register\", \"\", \"UREG.SGP0\")\n+DEF_ATTRIB(IMPLICIT_WRITES_SGP1, \"Writes SGP1 register\", \"\", \"UREG.SGP1\")\n+DEF_ATTRIB(IMPLICIT_WRITES_IMASK_ANYTHREAD,\n+ \"Writes IMASK for any thread\", \"\", \"\")\n+DEF_ATTRIB(IMPLICIT_WRITES_STID_PRIO_ANYTHREAD,\n+ \"Writes STID priority for any thread\", \"\", \"\")\n DEF_ATTRIB(COMMUTES, \"The operation is communitive\", \"\", \"\")\n DEF_ATTRIB(DEALLOCRET, \"dealloc_return\", \"\", \"\")\n DEF_ATTRIB(DEALLOCFRAME, \"deallocframe\", \"\", \"\")\n@@ -137,9 +161,15 @@ DEF_ATTRIB(RESTRICT_SLOT3ONLY, \"Must execute on slot3\", \"\", \"\")\n DEF_ATTRIB(RESTRICT_NOSLOT1, \"No slot 1 instruction in parallel\", \"\", \"\")\n DEF_ATTRIB(RESTRICT_PREFERSLOT0, \"Try to encode into slot 0\", \"\", \"\")\n DEF_ATTRIB(RESTRICT_PACKET_AXOK, \"May exist with A-type or X-type\", \"\", \"\")\n+DEF_ATTRIB(RESTRICT_SINGLE_MEM_FIRST, \"Single memory op must be first\", \"\", \"\")\n+DEF_ATTRIB(RESTRICT_SLOT1_AOK, \"Slot 1 is allowed\", \"\", \"\")\n \n DEF_ATTRIB(ICOP, \"Instruction cache op\", \"\", \"\")\n \n+DEF_ATTRIB(EXCEPTION_SWI, \"Software interrupt exception\", \"\", \"\")\n+DEF_ATTRIB(DMA, \"DMA instruction\", \"\", \"\")\n+DEF_ATTRIB(NO_TIMING_LOG, \"Does not get logged to the timing model\", \"\", \"\")\n+\n DEF_ATTRIB(HWLOOP0_END, \"Ends HW loop0\", \"\", \"\")\n DEF_ATTRIB(HWLOOP1_END, \"Ends HW loop1\", \"\", \"\")\n DEF_ATTRIB(RET_TYPE, \"return type\", \"\", \"\")\n@@ -151,6 +181,10 @@ DEF_ATTRIB(DCFETCH, \"dcfetch type\", \"\", \"\")\n \n DEF_ATTRIB(L2FETCH, \"Instruction is l2fetch type\", \"\", \"\")\n \n+DEF_ATTRIB(DCTAGOP, \"Data cache tag operation\", \"\", \"\")\n+DEF_ATTRIB(ICTAGOP, \"Instruction cache tag operation\", \"\", \"\")\n+DEF_ATTRIB(L2TAGOP, \"L2 cache tag operation\", \"\", \"\")\n+\n DEF_ATTRIB(ICINVA, \"icinva\", \"\", \"\")\n DEF_ATTRIB(DCCLEANINVA, \"dccleaninva\", \"\", \"\")\n \n@@ -166,6 +200,9 @@ DEF_ATTRIB(NOTE_LATEPRED, \"The predicate can not be used as a .new\", \"\", \"\")\n DEF_ATTRIB(NOTE_NVSLOT0, \"Can execute only in slot 0 (ST)\", \"\", \"\")\n DEF_ATTRIB(NOTE_NOVP, \"Cannot be paired with a HVX permute instruction\", \"\", \"\")\n DEF_ATTRIB(NOTE_VA_UNARY, \"Combined with HVX ALU op (must be unary)\", \"\", \"\")\n+DEF_ATTRIB(NOTE_SLOT1_AOK, \"Slot 1 is allowed\", \"\", \"\")\n+DEF_ATTRIB(NOTE_GUEST, \"Guest mode instruction\", \"\", \"\")\n+DEF_ATTRIB(NOTE_BADTAG_UNDEF, \"Bad tag results in undefined behavior\", \"\", \"\")\n \n /* V6 MMVector Notes for Documentation */\n DEF_ATTRIB(NOTE_SHIFT_RESOURCE, \"Uses the HVX shift resource.\", \"\", \"\")\ndiff --git a/target/hexagon/imported/macros.def b/target/hexagon/imported/macros.def\nold mode 100755\nnew mode 100644\nindex 4bbcfdd5e19..f24f89f3612\n--- a/target/hexagon/imported/macros.def\n+++ b/target/hexagon/imported/macros.def\n@@ -353,6 +353,12 @@ DEF_MACRO(\n ()\n )\n \n+DEF_MACRO(\n+ fREAD_SSR, /* read SSR register */\n+ (READ_RREG(REG_SSR)), /* behavior */\n+ ()\n+)\n+\n DEF_MACRO(\n fWRITE_LR, /* write lr */\n WRITE_RREG(REG_LR,A), /* behavior */\n@@ -371,12 +377,36 @@ DEF_MACRO(\n (A_IMPLICIT_WRITES_SP)\n )\n \n+DEF_MACRO(\n+ fWRITE_GOSP, /* write gosp */\n+ WRITE_RREG(REG_GOSP,A), /* behavior */\n+ (A_IMPLICIT_WRITES_GOSP)\n+)\n+\n DEF_MACRO(\n fREAD_SP, /* read stack pointer */\n (READ_RREG(REG_SP)), /* behavior */\n ()\n )\n \n+DEF_MACRO(\n+ fREAD_GOSP, /* read guest other stack pointer */\n+ (READ_RREG(REG_GOSP)), /* behavior */\n+ ()\n+)\n+\n+DEF_MACRO(\n+ fREAD_GELR, /* read guest other stack pointer */\n+ (READ_RREG(REG_GELR)), /* behavior */\n+ ()\n+)\n+\n+DEF_MACRO(\n+ fREAD_GEVB, /* read guest other stack pointer */\n+ (READ_RREG(REG_GEVB)), /* behavior */\n+ ()\n+)\n+\n DEF_MACRO(\n fREAD_CSREG, /* read CS register */\n (READ_RREG(REG_CSA+N)), /* behavior */\n@@ -570,6 +600,11 @@ DEF_MACRO(\n WRITE_PREG(3,VAL), /* behavior */\n (A_IMPLICIT_WRITES_P3)\n )\n+DEF_MACRO(\n+\tfWRITE_P3_LATE, /* write Predicate 0 */\n+\t{WRITE_PREG(3,VAL); fHIDE(MARK_LATE_PRED_WRITE(3))} , /* behavior */\n+\t(A_IMPLICIT_WRITES_P3,A_RESTRICT_LATEPRED)\n+)\n \n DEF_MACRO(\n fPART1, /* write Predicate 0 */\n@@ -660,6 +695,7 @@ DEF_MACRO(\n ((size8s_t)((size2s_t)(A))),\n /* optional attributes */\n )\n+\n DEF_MACRO(\n fCAST2_8u, /* macro name */\n ((size8u_t)((size2u_t)(A))),\n@@ -1532,18 +1568,209 @@ DEF_MACRO(fECHO,\n /* OS interface and stop/wait */\n /********************************************/\n \n+DEF_MACRO(RUNNABLE_THREADS_MAX,\n+ (thread->processor_ptr->runnable_threads_max),\n+ ()\n+)\n+\n+DEF_MACRO(THREAD_IS_ON,\n+ ((PROC->arch_proc_options->thread_enable_mask>>TNUM) & 0x1),\n+ ()\n+)\n+\n+DEF_MACRO(THREAD_EN_MASK,\n+ ((PROC->arch_proc_options->thread_enable_mask)),\n+ ()\n+)\n+\n+\n+\n+DEF_MACRO(READ_IMASK,\n+ (((TH) >= (thread->processor_ptr->runnable_threads_max)) ? 0 : (thread->processor_ptr->thread[TH]->Regs[REG_IMASK])),\n+ ()\n+)\n+DEF_MACRO(WRITE_IMASK,\n+ if ((TH) < (thread->processor_ptr->runnable_threads_max)) { thread->processor_ptr->thread[TH]->Regs[REG_IMASK]=(VAL & reg_mutability[REG_IMASK] ); },\n+ (A_IMPLICIT_WRITES_IMASK_ANYTHREAD)\n+)\n+\n+\n+DEF_MACRO(WRITE_PRIO,\n+ {\n+ if ((TH) < (thread->processor_ptr->runnable_threads_max)) {\n+ size4u_t tid_reg = thread->processor_ptr->thread[TH]->Regs[REG_TID];\n+ fINSERT_BITS(tid_reg, reg_field_info[STID_PRIO].width, reg_field_info[STID_PRIO].offset, VAL);\n+ LOG_OTHER_THREAD_REG_WRITE(thread,REG_TID,tid_reg,TH);\n+ }\n+ },\n+ (A_IMPLICIT_WRITES_STID_PRIO_ANYTHREAD)\n+)\n+\n+\n+DEF_MACRO(DO_IASSIGNW,\n+ {\n+ int i;\n+ int intbitpos = ((REG>>16)&0xF);\n+ for (i=0;i<RUNNABLE_THREADS_MAX;i++) {\n+ if(( (thread->processor_ptr->arch_proc_options->thread_enable_mask>>i) & 0x1)) {\n+ fINSERT_BITS(thread->processor_ptr->thread[i]->Regs[REG_IMASK],1, intbitpos, (REG>>i) & 1);\n+ }\n+ }\n+ },\n+ (A_IMPLICIT_WRITES_IMASK_ANYTHREAD)\n+)\n+\n+\n+\n+\n+DEF_MACRO(fDO_NMI,\n+ {\n+ int i;\n+ for (i=0;i<RUNNABLE_THREADS_MAX;i++) {\n+ if( ( (thread->processor_ptr->arch_proc_options->thread_enable_mask>>i) & 0x1) ) {\n+ if (SREG & (1<<i)) {\n+ register_nmi_interrupt(thread->processor_ptr->thread[i]);\n+ }\n+ }\n+ }\n+ },\n+)\n+\n+DEF_MACRO(fDO_TRACE,\n+ {\n+ fHIDE(HEX_CALLBACK(thread->processor_ptr->options->trace_callback,\n+ thread->system_ptr,thread->processor_ptr,\n+ thread->threadId,SREG);)\n+ },\n+)\n+\n+DEF_MACRO(DO_IASSIGNR,\n+ {\n+ int i;\n+ int result=0;\n+ int intbitpos = ((SREG>>16)&0xF);\n+ for (i=0;i<RUNNABLE_THREADS_MAX;i++) {\n+ if(( (thread->processor_ptr->arch_proc_options->thread_enable_mask>>i) & 0x1)) {\n+ result |= (((thread->processor_ptr->thread[i]->Regs[REG_IMASK]>>intbitpos)&1)<<i);\n+ }\n+ }\n+ DREG=result;\n+ },\n+ ()\n+)\n+\n+DEF_MACRO(DO_SWI,\n+ {fHIDE(HEX_CALLBACK(thread->processor_ptr->options->swi_callback,\n+ thread->system_ptr,thread->processor_ptr,\n+ thread->threadId,REG));\n+ LOG_GLOBAL_REG_WRITE(REG_IPEND,(GLOBAL_REG_READ(REG_IPEND) | (REG & GLOBAL_REG_READ(REG_IEL))));\n+ },\n+ (A_EXCEPTION_SWI)\n+)\n+\n+DEF_MACRO(DO_CSWI,\n+ LOG_GLOBAL_REG_WRITE(REG_IPEND,GLOBAL_REG_READ(REG_IPEND) & ~((REG) & GLOBAL_REG_READ(REG_IEL)));,\n+ ()\n+)\n+\n+DEF_MACRO(DO_CIAD,\n+ sys_ciad(thread,VAL); LOG_GLOBAL_REG_WRITE(REG_IAD,GLOBAL_REG_READ(REG_IAD) & ~(VAL));,\n+ (A_EXCEPTION_SWI)\n+)\n+\n+DEF_MACRO(DO_SIAD,\n+ sys_siad(thread,VAL); LOG_GLOBAL_REG_WRITE(REG_IAD,GLOBAL_REG_READ(REG_IAD) | (VAL));,\n+ (A_EXCEPTION_SWI)\n+)\n+\n+DEF_MACRO(fBREAK,\n+ {isdb_brkpt_insn(thread->processor_ptr,thread->threadId);},\n+ ()\n+)\n+\n DEF_MACRO(fPAUSE,\n {sys_pause(thread, insn->slot, IMM);},\n ()\n )\n \n+\n DEF_MACRO(fTRAP,\n warn(\"Trap NPC=%x \",fREAD_NPC());\n warn(\"Trap exception, PCYCLE=%lld TYPE=%d NPC=%x IMM=0x%x\",thread->processor_ptr->pstats[pcycles],TRAPTYPE,fREAD_NPC(),IMM);\n register_trap_exception(thread,fREAD_NPC(),TRAPTYPE,IMM);,\n+ (A_EXCEPTION_SWI)\n+)\n+\n+DEF_MACRO(fINTERNAL_CLEAR_SAMEPAGE,\n+ /* force re-xlate at next fetch, refresh of in_user_mode, etc */\n+ /* Permissions change too... */\n+ sys_utlb_invalidate(thread->processor_ptr,thread),\n+ /* NOTHING */\n+)\n+\n+DEF_MACRO(fCLEAR_RTE_EX,\n+ {\n+ fLOG_REG_FIELD(SSR,SSR_EX,0);\n+ fINTERNAL_CLEAR_SAMEPAGE();\n+ },\n+ ()\n+)\n+\n+DEF_MACRO(fTLB_LOCK_AVAILABLE,\n+ (fREAD_GLOBAL_REG_FIELD(SYSCONF,SYSCFG_TLBLOCK) == 0),\n ()\n )\n \n+DEF_MACRO(fK0_LOCK_AVAILABLE,\n+ (fREAD_GLOBAL_REG_FIELD(SYSCONF,SYSCFG_K0LOCK) == 0),\n+ ()\n+)\n+\n+DEF_MACRO(fSET_TLB_LOCK,\n+ {\n+ if (fTLB_LOCK_AVAILABLE()) {\n+ fLOG_GLOBAL_REG_FIELD(SYSCONF,SYSCFG_TLBLOCK,1);\n+ } else {\n+ sys_waiting_for_tlb_lock(thread);\n+ }\n+ },\n+ ()\n+)\n+\n+DEF_MACRO(fSET_K0_LOCK,\n+ {\n+ if (fK0_LOCK_AVAILABLE() && sys_k0lock_queue_ready(thread)) {\n+ warn(\"k0lock: T%d: PC=0x%x: PCycle=%lld\",thread->threadId,thread->Regs[REG_PC],thread->processor_ptr->pstats[pcycles]);\n+ fLOG_GLOBAL_REG_FIELD(SYSCONF,SYSCFG_K0LOCK,1);\n+ } else {\n+ warn(\"k0lock_waiting: T%d: PC=0x%x: PCycle=%lld\",thread->threadId,thread->Regs[REG_PC],thread->processor_ptr->pstats[pcycles]);\n+ sys_waiting_for_k0_lock(thread);\n+ }\n+ },\n+ ()\n+)\n+\n+DEF_MACRO(fCLEAR_TLB_LOCK,\n+ {\n+ int i;\n+ fLOG_GLOBAL_REG_FIELD(SYSCONF,SYSCFG_TLBLOCK,0);\n+ for (i = 0; i < RUNNABLE_THREADS_MAX; i++) {\n+ if(( (thread->processor_ptr->arch_proc_options->thread_enable_mask>>i) & 0x1)) {\n+ thread->processor_ptr->thread[i]->cu_tlb_lock_waiting = 0;\n+ }\n+ }\n+ },\n+ ()\n+)\n+\n+DEF_MACRO(fCLEAR_K0_LOCK,\n+ do {\n+ warn(\"k0unlock: T%d: PC=0x%x: Pcycle=%lld\",thread->threadId,thread->Regs[REG_PC], thread->processor_ptr->pstats[pcycles]);\n+ sys_initiate_clear_k0_lock(thread);\n+ } while (0),\n+ ()\n+)\n+\n DEF_MACRO(fALIGN_REG_FIELD_VALUE,\n ((VAL)<<reg_field_info[FIELD].offset),\n /* */\n@@ -1554,6 +1781,26 @@ DEF_MACRO(fGET_REG_FIELD_MASK,\n /* */\n )\n \n+DEF_MACRO(fLOG_REG_FIELD,\n+ LOG_MASKED_REG_WRITE(thread,REG_##REG,\n+ fALIGN_REG_FIELD_VALUE(FIELD,VAL),\n+ fGET_REG_FIELD_MASK(FIELD)),\n+ ()\n+)\n+\n+DEF_MACRO(fWRITE_GLOBAL_REG_FIELD,\n+ fINSERT_BITS(thread->processor_ptr->global_regs[REG_##REG],\n+ reg_field_info[FIELD].width,\n+ reg_field_info[FIELD].offset,VAL),\n+)\n+\n+DEF_MACRO(fLOG_GLOBAL_REG_FIELD,\n+ LOG_MASKED_GLOBAL_REG_WRITE(REG_##REG,\n+ fALIGN_REG_FIELD_VALUE(FIELD,VAL),\n+ fGET_REG_FIELD_MASK(FIELD)),\n+ ()\n+)\n+\n DEF_MACRO(fREAD_REG_FIELD,\n fEXTRACTU_BITS(thread->Regs[REG_##REG],\n reg_field_info[FIELD].width,\n@@ -1561,6 +1808,13 @@ DEF_MACRO(fREAD_REG_FIELD,\n /* ATTRIBS */\n )\n \n+DEF_MACRO(fREAD_GLOBAL_REG_FIELD,\n+ fEXTRACTU_BITS(thread->processor_ptr->global_regs[REG_##REG],\n+ reg_field_info[FIELD].width,\n+ reg_field_info[FIELD].offset),\n+ /* ATTRIBS */\n+)\n+\n DEF_MACRO(fGET_FIELD,\n fEXTRACTU_BITS(VAL,\n reg_field_info[FIELD].width,\n@@ -1576,6 +1830,185 @@ DEF_MACRO(fSET_FIELD,\n /* ATTRIBS */\n )\n \n+DEF_MACRO(fSET_RUN_MODE_NOW,\n+ {thread->processor_ptr->global_regs[REG_MODECTL] |= (1<<TNUM);\n+ thread->last_commit_cycle = thread->processor_ptr->pcycle_counter;\n+ sys_recalc_num_running_threads(thread->processor_ptr);},\n+)\n+\n+DEF_MACRO(fIN_DEBUG_MODE,\n+ (thread->debug_mode || (fREAD_GLOBAL_REG_FIELD(ISDBST,ISDBST_DEBUGMODE) & 1<<TNUM)),\n+ ()\n+)\n+DEF_MACRO(fIN_DEBUG_MODE_NO_ISDB,\n+ (thread->debug_mode),\n+ ()\n+)\n+\n+\n+DEF_MACRO(fIN_DEBUG_MODE_WARN,\n+ {\n+ if (fREAD_GLOBAL_REG_FIELD(ISDBST,ISDBST_DEBUGMODE) & 1<<TNUM)\n+ warn(\"In ISDB debug mode, but TB told me to step normally\");\n+ },\n+ ()\n+)\n+\n+DEF_MACRO(fCLEAR_RUN_MODE,\n+ {fLOG_GLOBAL_REG_FIELD(MODECTL,MODECTL_E,\n+ fREAD_GLOBAL_REG_FIELD(MODECTL,MODECTL_E) & ~(1<<(TNUM)))},\n+ /* NOTHING */\n+)\n+\n+DEF_MACRO(fCLEAR_RUN_MODE_NOW,\n+ do {\n+ fWRITE_GLOBAL_REG_FIELD(MODECTL,MODECTL_E,\n+ fREAD_GLOBAL_REG_FIELD(MODECTL,MODECTL_E) & ~(1<<(TNUM)));\n+ sys_recalc_num_running_threads(thread->processor_ptr);\n+ } while (0),\n+ /* NOTHING */\n+)\n+\n+DEF_MACRO(fGET_RUN_MODE,\n+ ((thread->processor_ptr->global_regs[REG_MODECTL]>>TNUM)&0x1),\n+)\n+\n+DEF_MACRO(fSET_WAIT_MODE,\n+ {fLOG_GLOBAL_REG_FIELD(MODECTL,MODECTL_W,\n+ fREAD_GLOBAL_REG_FIELD(MODECTL,MODECTL_W) | 1<<(TNUM))},\n+ /* NOTHING */\n+)\n+\n+DEF_MACRO(fCLEAR_WAIT_MODE,\n+ {thread->processor_ptr->global_regs[REG_MODECTL] &= ~(1<<(TNUM+16));\n+ thread->last_commit_cycle = thread->processor_ptr->pcycle_counter;\n+ sys_recalc_num_running_threads(thread->processor_ptr);},\n+)\n+\n+DEF_MACRO(fGET_WAIT_MODE,\n+ ((thread->processor_ptr->global_regs[REG_MODECTL]>>(TNUM+16))&0x1),\n+)\n+\n+\n+DEF_MACRO(fRESET_THREAD,\n+ register_reset_interrupt(T,NUM),\n+)\n+\n+DEF_MACRO(fREAD_CURRENT_EVB,\n+ (GLOBAL_REG_READ(REG_EVB)),\n+ /* nothing */\n+)\n+\n+DEF_MACRO(fREAD_ELR,\n+ READ_RREG(REG_ELR),\n+ ()\n+)\n+\n+DEF_MACRO(fPOW2_HELP_ROUNDUP,\n+ ((VAL) | ((VAL) >> 1) | ((VAL) >> 2) | ((VAL) >> 4) | ((VAL) >> 8) | ((VAL) >> 16)),\n+ ()\n+)\n+\n+DEF_MACRO(fPOW2_ROUNDUP,\n+ fPOW2_HELP_ROUNDUP((VAL)-1)+1,\n+ ()\n+)\n+\n+DEF_MACRO(fTLB_IDXMASK,\n+ ((INDEX) & (fPOW2_ROUNDUP(fCAST4u(thread->processor_ptr->arch_proc_options->jtlb_size)) - 1)),\n+ ()\n+)\n+\n+DEF_MACRO(fTLB_NONPOW2WRAP,\n+ (((INDEX) >= thread->processor_ptr->arch_proc_options->jtlb_size) ? ((INDEX) - thread->processor_ptr->arch_proc_options->jtlb_size) : (INDEX)),\n+ /* ATTRIBS */\n+)\n+\n+DEF_MACRO(fTLBW,\n+ do {size4u_t __myidx = fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX));\n+ TLB_REG_WRITE(__myidx,VALUE);\n+ fHIDE(HEX_CALLBACK(thread->processor_ptr->options->tlbw_callback,thread->system_ptr,thread->processor_ptr,thread->threadId,__myidx);)\n+ fHIDE(sys_tlb_write(thread,__myidx,VALUE);)} while (0),\n+ /* ATTRIBS */\n+)\n+\n+DEF_MACRO(fTLB_ENTRY_OVERLAP,\n+ fHIDE( (sys_check_overlap(thread,VALUE)!=-2) ),\n+ /* ATTRIBS */\n+)\n+\n+DEF_MACRO(fTLB_ENTRY_OVERLAP_IDX,\n+ fHIDE(sys_check_overlap(thread,VALUE)),\n+ /* ATTRIBS */\n+)\n+\n+\n+DEF_MACRO(fTLBR,\n+ TLB_REG_READ(fTLB_NONPOW2WRAP(fTLB_IDXMASK(INDEX))),\n+ /* ATTRIBS */\n+)\n+\n+DEF_MACRO(fTLBP,\n+ tlb_lookup(thread,((TLBHI)>>12),((TLBHI)<<12),1),\n+ /* attribs */\n+)\n+\n+\n+\n+DEF_MACRO(READ_SGP0,\n+ READ_RREG(REG_SGP),\n+ ()\n+)\n+\n+DEF_MACRO(READ_SGP1,\n+ READ_RREG(REG_SGP+1),\n+ ()\n+)\n+\n+DEF_MACRO(READ_SGP10,\n+ READ_RREG_PAIR(REG_SGP),\n+ ()\n+)\n+\n+DEF_MACRO(READ_UGP,\n+ READ_RREG(REG_UGP),\n+)\n+\n+DEF_MACRO(WRITE_SGP0,\n+ WRITE_RREG(REG_SGP,VAL),\n+ (A_IMPLICIT_WRITES_SGP0)\n+)\n+\n+DEF_MACRO(WRITE_SGP1,\n+ WRITE_RREG(REG_SGP+1,VAL),\n+ (A_IMPLICIT_WRITES_SGP1)\n+)\n+\n+DEF_MACRO(WRITE_SGP10,\n+ WRITE_RREG_PAIR(REG_SGP,VAL),\n+ (A_IMPLICIT_WRITES_SGP0,A_IMPLICIT_WRITES_SGP1)\n+)\n+\n+DEF_MACRO(WRITE_UGP,\n+ WRITE_RREG(REG_UGP,VAL),\n+)\n+\n+DEF_MACRO(fSTART,\n+ fLOG_GLOBAL_REG_FIELD(MODECTL,MODECTL_E, fREAD_GLOBAL_REG_FIELD(MODECTL,MODECTL_E) | (((REG & ((1<<RUNNABLE_THREADS_MAX)-1))) & THREAD_EN_MASK(thread->processor_ptr))),\n+ ()\n+)\n+\n+DEF_MACRO(fRESUME,\n+ fLOG_GLOBAL_REG_FIELD(MODECTL,MODECTL_W,\n+ fREAD_GLOBAL_REG_FIELD(MODECTL,MODECTL_W) & (~(REG))),\n+ ()\n+)\n+\n+DEF_MACRO(fGET_TNUM,\n+ thread->threadId,\n+ ()\n+)\n+\n /********************************************/\n /* Cache Management */\n /********************************************/\n@@ -1602,6 +2035,11 @@ DEF_MACRO(fISYNC,\n )\n \n \n+DEF_MACRO(fICFETCH,\n+ ,\n+ ()\n+)\n+\n DEF_MACRO(fDCFETCH,\n sys_dcfetch(thread, (REG), insn->slot),\n (A_MEMLIKE)\n@@ -1615,6 +2053,34 @@ DEF_MACRO(fICINVA,\n (A_ICINVA)\n )\n \n+DEF_MACRO(fDCTAGR,\n+ ({DST=sys_dctagr(thread, INDEX, insn->slot,DSTREGNO);})/* FIXME */,\n+ ()\n+)\n+\n+DEF_MACRO(fDCTAGW,\n+ (sys_dctagw(thread, INDEX, PART2, insn->slot)),\n+ ()\n+)\n+DEF_MACRO(fICTAGR,\n+ ({DST=sys_ictagr(thread, INDEX, insn->slot,REGNO);}),\n+ ()\n+)\n+\n+DEF_MACRO(fICDATAR,\n+ ({DST=sys_icdatar(thread, INDEX, insn->slot);}),\n+ ()\n+)\n+\n+DEF_MACRO(fICTAGW,\n+ (sys_ictagw(thread, INDEX, PART2, insn->slot)),\n+ ()\n+)\n+DEF_MACRO(fICDATAW,\n+ ({ fHIDE(); }),\n+ ()\n+)\n+\n DEF_MACRO(fL2FETCH,\n sys_l2fetch(thread, ADDR,HEIGHT,WIDTH,STRIDE,FLAGS, insn->slot),\n (A_MEMLIKE,A_L2FETCH)\n@@ -1635,6 +2101,12 @@ DEF_MACRO(fDCZEROA,\n (A_MEMLIKE)\n )\n \n+DEF_MACRO(fDCINVA,\n+ sys_dcinva(thread, (REG)),\n+ (A_MEMLIKE)\n+)\n+\n+\n DEF_MACRO(fCHECKFORPRIV,\n {sys_check_privs(thread); if (EXCEPTION_DETECTED) return; },\n ()\n@@ -1645,6 +2117,16 @@ DEF_MACRO(fCHECKFORGUEST,\n ()\n )\n \n+DEF_MACRO(fTAKEN_INTERRUPT_EDGECLEAR,\n+ { proc->global_regs[REG_IPEND] &= ~(INT_NUMTOMASK(intnum) & proc->global_regs[REG_IEL]); },\n+ ()\n+)\n+\n+DEF_MACRO(fSET_IAD,\n+ { sys_siad(thread,INT_NUMTOMASK(intnum)); thread->processor_ptr->global_regs[REG_IAD] |= INT_NUMTOMASK(intnum); },\n+ ()\n+)\n+\n DEF_MACRO(fBRANCH_SPECULATE_STALL,\n {\n sys_speculate_branch_stall(thread, insn->slot, JUMP_COND(JUMP_PRED_SET),\n@@ -1664,3 +2146,79 @@ DEF_MACRO(IV1DEAD,\n ,\n ()\n )\n+\n+DEF_MACRO(fIN_MONITOR_MODE,\n+ sys_in_monitor_mode(thread),\n+ ()\n+)\n+\n+DEF_MACRO(fIN_USER_MODE,\n+ sys_in_user_mode(thread),\n+ ()\n+)\n+\n+DEF_MACRO(fIN_GUEST_MODE,\n+ sys_in_guest_mode(thread),\n+ ()\n+)\n+\n+DEF_MACRO(fGRE_ENABLED,\n+ fREAD_REG_FIELD(CCR,CCR_GRE),\n+ ()\n+)\n+\n+DEF_MACRO(fGTE_ENABLED,\n+ fREAD_REG_FIELD(CCR,CCR_GRE),\n+ ()\n+)\n+\n+DEF_MACRO(fTRAP1_VIRTINSN,\n+ ((fIN_GUEST_MODE())\n+ && (fGRE_ENABLED())\n+ && ( ((IMM) == 1)\n+ || ((IMM) == 3)\n+ || ((IMM) == 4)\n+ || ((IMM) == 6))),\n+ ()\n+)\n+\n+DEF_MACRO(fVIRTINSN_RTE,\n+ do {\n+ thread->trap1_info = TRAP1_VIRTINSN_RTE;\n+ fLOG_REG_FIELD(SSR,SSR_SS,fREAD_REG_FIELD(GSR,GSR_SS));\n+ fLOG_REG_FIELD(CCR,CCR_GIE,fREAD_REG_FIELD(GSR,GSR_IE));\n+ fLOG_REG_FIELD(SSR,SSR_GM,!fREAD_REG_FIELD(GSR,GSR_UM));\n+ fBRANCH((fREAD_GELR() & -4),COF_TYPE_RTE);\n+ fINTERNAL_CLEAR_SAMEPAGE();\n+ } while (0),\n+ (A_IMPLICIT_WRITES_CCR,A_IMPLICIT_WRITES_SSR)\n+)\n+\n+DEF_MACRO(fVIRTINSN_SETIE,\n+ do {\n+ fLOG_REG_FIELD(CCR,CCR_GIE,(REG) & 1);\n+ REG = fREAD_REG_FIELD(CCR,CCR_GIE);\n+ thread->trap1_info = TRAP1_VIRTINSN_SETIE;\n+ } while (0),\n+ (A_IMPLICIT_WRITES_CCR)\n+)\n+\n+DEF_MACRO(fVIRTINSN_GETIE,\n+ {\n+ thread->trap1_info = TRAP1_VIRTINSN_GETIE;\n+ REG = fREAD_REG_FIELD(CCR,CCR_GIE);\n+ },\n+ ()\n+)\n+\n+DEF_MACRO(fVIRTINSN_SPSWAP,\n+ do {\n+ if (fREAD_REG_FIELD(GSR,GSR_UM)) {\n+ size4u_t TEMP = REG;\n+ REG = fREAD_GOSP();\n+ fWRITE_GOSP(TEMP);\n+ thread->trap1_info = TRAP1_VIRTINSN_SPSWAP;\n+ }\n+ } while (0),\n+ (A_IMPLICIT_WRITES_GOSP)\n+)\n", "prefixes": [ "v3", "16/37" ] }