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GET /api/patches/2202567/?format=api
{ "id": 2202567, "url": "http://patchwork.ozlabs.org/api/patches/2202567/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-31-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227203627.932864-31-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-27T20:36:20", "name": "[v3,30/37] target/hexagon: Add sreg_{read,write} helpers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "deea07777da1ae605b53e541e7a3f72686c087c7", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-31-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 493813, "url": "http://patchwork.ozlabs.org/api/series/493813/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493813", "date": "2026-02-27T20:35:57", "name": "Hexagon system emulation - Part 1/3", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/493813/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2202567/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2202567/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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<sidneym@quicinc.com>", "Subject": "[PATCH v3 30/37] target/hexagon: Add sreg_{read,write} helpers", "Date": "Fri, 27 Feb 2026 12:36:20 -0800", "Message-Id": "<20260227203627.932864-31-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260227203627.932864-1-brian.cain@oss.qualcomm.com>", "References": "<20260227203627.932864-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Authority-Analysis": "v=2.4 cv=RPq+3oi+ c=1 sm=1 tr=0 ts=69a20078 cx=c_pps\n a=yymyAM/LQ7lj/HqAiIiKTw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22\n a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=_Ci8evVdfDH29BE0TZkA:9 a=QEXdDO2ut3YA:10\n a=efpaJB4zofY2dbm2aIRb:22 a=TjNXssC_j7lpFel5tvFf:22", "X-Proofpoint-ORIG-GUID": "cAVUsjd8GokIbzgdGkto9QPXtDoJbG7y", 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priorityscore=1501 malwarescore=0 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602270181", "Received-SPF": "pass client-ip=205.220.168.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.706,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.401, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nCo-authored-by: Sid Manning <sidneym@quicinc.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu_helper.h | 8 +++++\n target/hexagon/helper.h | 3 +-\n target/hexagon/cpu.c | 1 -\n target/hexagon/cpu_helper.c | 70 +++++++++++++++++++++++++++++++++++++\n target/hexagon/op_helper.c | 28 ++++++++++-----\n target/hexagon/meson.build | 1 +\n 6 files changed, 100 insertions(+), 11 deletions(-)\n create mode 100644 target/hexagon/cpu_helper.c", "diff": "diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h\nindex 8c79a4cea13..3d7238c3b06 100644\n--- a/target/hexagon/cpu_helper.h\n+++ b/target/hexagon/cpu_helper.h\n@@ -7,6 +7,14 @@\n #ifndef HEXAGON_CPU_HELPER_H\n #define HEXAGON_CPU_HELPER_H\n \n+uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index);\n+uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env);\n+uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env);\n+uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env);\n+void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t);\n+void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t);\n+void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t);\n+\n static inline void arch_set_thread_reg(CPUHexagonState *env, uint32_t reg,\n uint32_t val)\n {\ndiff --git a/target/hexagon/helper.h b/target/hexagon/helper.h\nindex 04c01649683..9ca87acfe63 100644\n--- a/target/hexagon/helper.h\n+++ b/target/hexagon/helper.h\n@@ -121,8 +121,7 @@ DEF_HELPER_2(sreg_read, i32, env, i32)\n DEF_HELPER_2(sreg_read_pair, i64, env, i32)\n DEF_HELPER_2(greg_read, i32, env, i32)\n DEF_HELPER_2(greg_read_pair, i64, env, i32)\n-DEF_HELPER_3(sreg_write, void, env, i32, i32)\n-DEF_HELPER_3(sreg_write_pair, void, env, i32, i64)\n+DEF_HELPER_3(sreg_write_masked, void, env, i32, i32)\n DEF_HELPER_3(setprio, void, env, i32, i32)\n DEF_HELPER_2(start, void, env, i32)\n DEF_HELPER_1(stop, void, env)\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex a8f2f9e238a..1010fa866b5 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -338,7 +338,6 @@ static void hexagon_cpu_realize(DeviceState *dev, Error **errp)\n \n qemu_init_vcpu(cs);\n cpu_reset(cs);\n-\n mcc->parent_realize(dev, errp);\n }\n \ndiff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c\nnew file mode 100644\nindex 00000000000..8e11cbb20dd\n--- /dev/null\n+++ b/target/hexagon/cpu_helper.c\n@@ -0,0 +1,70 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"cpu.h\"\n+#include \"cpu_helper.h\"\n+#include \"system/cpus.h\"\n+#ifdef CONFIG_USER_ONLY\n+#include \"qemu.h\"\n+#include \"exec/helper-proto.h\"\n+#else\n+#include \"hw/core/boards.h\"\n+#include \"hw/hexagon/hexagon.h\"\n+#endif\n+#include \"exec/cpu-interrupt.h\"\n+#include \"exec/target_page.h\"\n+#include \"accel/tcg/cpu-ldst.h\"\n+#include \"exec/cputlb.h\"\n+#include \"qemu/log.h\"\n+#include \"tcg/tcg-op.h\"\n+#include \"internal.h\"\n+#include \"macros.h\"\n+#include \"sys_macros.h\"\n+#include \"arch.h\"\n+\n+\n+#ifndef CONFIG_USER_ONLY\n+\n+uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index)\n+{\n+ g_assert_not_reached();\n+}\n+\n+uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env)\n+{\n+ g_assert_not_reached();\n+}\n+\n+uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env)\n+{\n+ g_assert_not_reached();\n+}\n+\n+uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env)\n+{\n+ g_assert_not_reached();\n+}\n+\n+void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env,\n+ uint32_t cycles_hi)\n+{\n+ g_assert_not_reached();\n+}\n+\n+void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env,\n+ uint32_t cycles_lo)\n+{\n+ g_assert_not_reached();\n+}\n+\n+void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t cycles)\n+{\n+ g_assert_not_reached();\n+}\n+\n+\n+#endif\ndiff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c\nindex 6754c491ff5..9b9655da961 100644\n--- a/target/hexagon/op_helper.c\n+++ b/target/hexagon/op_helper.c\n@@ -19,9 +19,10 @@\n #include \"qemu/log.h\"\n #include \"accel/tcg/cpu-ldst.h\"\n #include \"accel/tcg/probe.h\"\n+#include \"qemu/main-loop.h\"\n+#include \"cpu.h\"\n #include \"exec/helper-proto.h\"\n #include \"fpu/softfloat.h\"\n-#include \"cpu.h\"\n #include \"internal.h\"\n #include \"macros.h\"\n #include \"sys_macros.h\"\n@@ -1451,25 +1452,36 @@ void HELPER(setimask)(CPUHexagonState *env, uint32_t pred, uint32_t imask)\n g_assert_not_reached();\n }\n \n-void HELPER(sreg_write)(CPUHexagonState *env, uint32_t reg, uint32_t val)\n+void HELPER(sreg_write_masked)(CPUHexagonState *env, uint32_t reg, uint32_t val)\n {\n- g_assert_not_reached();\n+ BQL_LOCK_GUARD();\n+ arch_set_system_reg_masked(env, reg, val);\n }\n \n-void HELPER(sreg_write_pair)(CPUHexagonState *env, uint32_t reg, uint64_t val)\n-\n+static inline QEMU_ALWAYS_INLINE uint32_t sreg_read(CPUHexagonState *env,\n+ uint32_t reg)\n {\n- g_assert_not_reached();\n+ g_assert(bql_locked());\n+ if (reg < HEX_SREG_GLB_START) {\n+ return env->t_sreg[reg];\n+ }\n+ HexagonCPU *cpu = env_archcpu(env);\n+ return cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, reg, env->threadId) : 0;\n }\n \n uint32_t HELPER(sreg_read)(CPUHexagonState *env, uint32_t reg)\n {\n- g_assert_not_reached();\n+ BQL_LOCK_GUARD();\n+ return sreg_read(env, reg);\n }\n \n uint64_t HELPER(sreg_read_pair)(CPUHexagonState *env, uint32_t reg)\n {\n- g_assert_not_reached();\n+ BQL_LOCK_GUARD();\n+\n+ return deposit64((uint64_t) sreg_read(env, reg), 32, 32,\n+ sreg_read(env, reg + 1));\n }\n \n uint32_t HELPER(greg_read)(CPUHexagonState *env, uint32_t reg)\ndiff --git a/target/hexagon/meson.build b/target/hexagon/meson.build\nindex 528beca3cd0..9aabf5dd3c1 100644\n--- a/target/hexagon/meson.build\n+++ b/target/hexagon/meson.build\n@@ -240,6 +240,7 @@ hexagon_ss.add(files(\n 'cpu.c',\n 'translate.c',\n 'op_helper.c',\n+ 'cpu_helper.c',\n 'gdbstub.c',\n 'genptr.c',\n 'reg_fields.c',\n", "prefixes": [ "v3", "30/37" ] }