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GET /api/patches/2202553/?format=api
{ "id": 2202553, "url": "http://patchwork.ozlabs.org/api/patches/2202553/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-23-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227203627.932864-23-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-27T20:36:12", "name": "[v3,22/37] target/hexagon: Define register fields for system regs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a33b940b7d779865f8dad12a6c9d6ec30e1be9dc", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-23-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 493813, "url": "http://patchwork.ozlabs.org/api/series/493813/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493813", "date": "2026-02-27T20:35:57", "name": "Hexagon system emulation - Part 1/3", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/493813/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2202553/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2202553/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ku+CMhEG;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=P+BZENPS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjI3MDE4MSBTYWx0ZWRfXwPJHqJ+vs1GX\n dZf/JbKsoJ1fD762OUlgmqBykfnuUMybIaWWXUt25j8X4ec+zRc6i16TeN65ErwL+s2TS4zkebF\n j2eEMXqTD67N66K2NYmodUNlDh00wCVHorHbtaAECOlC01A9cWHvG2EOqzLhsszQeYF1SoZNDG5\n h9atX8R2YdWUck3i97RCx9IYMx6lg2mboIyEpdqTNY0ttfWXuVHXhIyTm45hL2b5/2bjKmbrYJA\n eFwTRbTBpC6AnxUPTzhFobILNEzBS6m7tLZP3rByUWT0M0CdI9c8ioTIiU0+cPpvO4VjUdiLfqt\n zTpr44dh7Rs8QRcCXU0H0/VN1TiDgAYsyJb2xTpHUWRmSuBHDI6fQDx6pOrzgbL8eNkXcN0d9GE\n bKUTsIqxXyCLseFTBfVJ0NRr3/spJg3OUtqphOFeoKz7Or3c4hl9DGmmAMK79i1rhLtDqDyDzIv\n il7ziTqJCEtG3jrctVw==", "X-Authority-Analysis": "v=2.4 cv=KL9XzVFo c=1 sm=1 tr=0 ts=69a2006f cx=c_pps\n a=z9lCQkyTxNhZyzAvolXo/A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22\n a=COk6AnOGAAAA:8 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=mmKuwxttERDeH49ycpoA:9\n a=QEXdDO2ut3YA:10 a=EyFUmsFV_t8cxB2kMr4A:22 a=TjNXssC_j7lpFel5tvFf:22", "X-Proofpoint-ORIG-GUID": "q0jjkWfUFnebro_wNCM5NuLNEYHd2h9N", "X-Proofpoint-GUID": "q0jjkWfUFnebro_wNCM5NuLNEYHd2h9N", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-27_04,2026-02-27_03,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0\n bulkscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602270181", "Received-SPF": "pass client-ip=205.220.180.131;\n envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.706,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.401, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nDefine the register fields for ssr, schedcfg, stid, bestwait, ccr,\nmodectl, imask, ipendad.\n\nDefine the fields for TLB entries.\n\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/reg_fields_def.h.inc | 96 +++++++++++++++++++++++++++++\n 1 file changed, 96 insertions(+)", "diff": "diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_fields_def.h.inc\nindex f2a58d486c5..9b112ccec64 100644\n--- a/target/hexagon/reg_fields_def.h.inc\n+++ b/target/hexagon/reg_fields_def.h.inc\n@@ -39,3 +39,99 @@ DEF_REG_FIELD(USR_FPDBZE, 26, 1)\n DEF_REG_FIELD(USR_FPOVFE, 27, 1)\n DEF_REG_FIELD(USR_FPUNFE, 28, 1)\n DEF_REG_FIELD(USR_FPINPE, 29, 1)\n+\n+DEF_REG_FIELD(IPENDAD_IAD, 16, 16)\n+DEF_REG_FIELD(IPENDAD_IPEND, 0, 16)\n+\n+DEF_REG_FIELD(SCHEDCFG_EN, 8, 1)\n+DEF_REG_FIELD(SCHEDCFG_INTNO, 0, 4)\n+DEF_REG_FIELD(BESTWAIT_PRIO, 0, 9)\n+\n+\n+/* PTE (aka TLB entry) fields */\n+DEF_REG_FIELD(PTE_PPD, 0, 24)\n+DEF_REG_FIELD(PTE_C, 24, 4)\n+DEF_REG_FIELD(PTE_U, 28, 1)\n+DEF_REG_FIELD(PTE_R, 29, 1)\n+DEF_REG_FIELD(PTE_W, 30, 1)\n+DEF_REG_FIELD(PTE_X, 31, 1)\n+DEF_REG_FIELD(PTE_VPN, 32, 20)\n+DEF_REG_FIELD(PTE_ASID, 52, 7)\n+DEF_REG_FIELD(PTE_ATR0, 59, 1)\n+DEF_REG_FIELD(PTE_ATR1, 60, 1)\n+DEF_REG_FIELD(PTE_PA35, 61, 1)\n+DEF_REG_FIELD(PTE_G, 62, 1)\n+DEF_REG_FIELD(PTE_V, 63, 1)\n+\n+/* SYSCFG fields */\n+DEF_REG_FIELD(SYSCFG_MMUEN, 0, 1)\n+DEF_REG_FIELD(SYSCFG_ICEN, 1, 1)\n+DEF_REG_FIELD(SYSCFG_DCEN, 2, 1)\n+DEF_REG_FIELD(SYSCFG_ISDBTRUSTED, 3, 1)\n+DEF_REG_FIELD(SYSCFG_GIE, 4, 1)\n+DEF_REG_FIELD(SYSCFG_ISDBREADY, 5, 1)\n+DEF_REG_FIELD(SYSCFG_PCYCLEEN, 6, 1)\n+DEF_REG_FIELD(SYSCFG_V2X, 7, 1)\n+DEF_REG_FIELD(SYSCFG_IGNOREDABORT, 8, 1)\n+DEF_REG_FIELD(SYSCFG_PM, 9, 1)\n+DEF_REG_FIELD(SYSCFG_TLBLOCK, 11, 1)\n+DEF_REG_FIELD(SYSCFG_K0LOCK, 12, 1)\n+DEF_REG_FIELD(SYSCFG_BQ, 13, 1)\n+DEF_REG_FIELD(SYSCFG_PRIO, 14, 1)\n+DEF_REG_FIELD(SYSCFG_DMT, 15, 1)\n+DEF_REG_FIELD(SYSCFG_L2CFG, 16, 3)\n+DEF_REG_FIELD(SYSCFG_ITCM, 19, 1)\n+DEF_REG_FIELD(SYSCFG_L2NWA, 21, 1)\n+DEF_REG_FIELD(SYSCFG_L2NRA, 22, 1)\n+DEF_REG_FIELD(SYSCFG_L2WB, 23, 1)\n+DEF_REG_FIELD(SYSCFG_L2P, 24, 1)\n+DEF_REG_FIELD(SYSCFG_SLVCTL0, 25, 2)\n+DEF_REG_FIELD(SYSCFG_SLVCTL1, 27, 2)\n+DEF_REG_FIELD(SYSCFG_L2PARTSIZE, 29, 2)\n+DEF_REG_FIELD(SYSCFG_L2GCA, 31, 1)\n+\n+/* SSR fields */\n+DEF_REG_FIELD(SSR_CAUSE, 0, 8)\n+DEF_REG_FIELD(SSR_ASID, 8, 7)\n+DEF_REG_FIELD(SSR_UM, 16, 1)\n+DEF_REG_FIELD(SSR_EX, 17, 1)\n+DEF_REG_FIELD(SSR_IE, 18, 1)\n+DEF_REG_FIELD(SSR_GM, 19, 1)\n+DEF_REG_FIELD(SSR_V0, 20, 1)\n+DEF_REG_FIELD(SSR_V1, 21, 1)\n+DEF_REG_FIELD(SSR_BVS, 22, 1)\n+DEF_REG_FIELD(SSR_CE, 23, 1)\n+DEF_REG_FIELD(SSR_PE, 24, 1)\n+DEF_REG_FIELD(SSR_BP, 25, 1)\n+DEF_REG_FIELD(SSR_XE2, 26, 1)\n+DEF_REG_FIELD(SSR_XA, 27, 3)\n+DEF_REG_FIELD(SSR_SS, 30, 1)\n+DEF_REG_FIELD(SSR_XE, 31, 1)\n+\n+/* misc registers */\n+DEF_REG_FIELD(IMASK_MASK, 0, 16)\n+\n+DEF_REG_FIELD(STID_PRIO, 16, 8)\n+DEF_REG_FIELD(STID_STID, 0, 8)\n+\n+/* MODECTL fields */\n+DEF_REG_FIELD(MODECTL_E, 0, 8)\n+DEF_REG_FIELD(MODECTL_W, 16, 8)\n+\n+DEF_REG_FIELD(CCR_L1ICP, 0, 2)\n+DEF_REG_FIELD(CCR_L1DCP, 3, 2)\n+DEF_REG_FIELD(CCR_L2CP, 6, 2)\n+\n+DEF_REG_FIELD(CCR_HFI, 16, 1)\n+DEF_REG_FIELD(CCR_HFD, 17, 1)\n+DEF_REG_FIELD(CCR_HFIL2, 18, 1)\n+DEF_REG_FIELD(CCR_HFDL2, 19, 1)\n+DEF_REG_FIELD(CCR_SFD, 20, 1)\n+\n+DEF_REG_FIELD(CCR_GIE, 24, 1)\n+DEF_REG_FIELD(CCR_GTE, 25, 1)\n+DEF_REG_FIELD(CCR_GEE, 26, 1)\n+DEF_REG_FIELD(CCR_GRE, 27, 1)\n+DEF_REG_FIELD(CCR_VV1, 29, 1)\n+DEF_REG_FIELD(CCR_VV2, 30, 1)\n+DEF_REG_FIELD(CCR_VV3, 31, 1)\n", "prefixes": [ "v3", "22/37" ] }