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GET /api/patches/2202547/?format=api
{ "id": 2202547, "url": "http://patchwork.ozlabs.org/api/patches/2202547/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-2-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227203627.932864-2-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-27T20:35:51", "name": "[v3,01/37] docs: Add hexagon sysemu docs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1be9600164a1f7674a88ff8676876d6d1bdabb99", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-2-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 493813, "url": "http://patchwork.ozlabs.org/api/series/493813/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493813", "date": "2026-02-27T20:35:57", "name": "Hexagon system emulation - Part 1/3", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/493813/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2202547/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2202547/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=YCd6ROmT;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=MwehHyyt;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.706,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.401, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n MAINTAINERS | 3 +\n docs/devel/hexagon-sys.rst | 112 +++++++++++++++++++++++++++++++++\n docs/devel/index-internals.rst | 1 +\n docs/system/hexagon/cdsp.rst | 12 ++++\n docs/system/target-hexagon.rst | 102 ++++++++++++++++++++++++++++++\n docs/system/targets.rst | 1 +\n 6 files changed, 231 insertions(+)\n create mode 100644 docs/devel/hexagon-sys.rst\n create mode 100644 docs/system/hexagon/cdsp.rst\n create mode 100644 docs/system/target-hexagon.rst", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex e0c481e2125..69cb6b8a7b5 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -246,6 +246,9 @@ F: disas/hexagon.c\n F: configs/targets/hexagon-linux-user/default.mak\n F: docker/dockerfiles/debian-hexagon-cross.docker\n F: gdb-xml/hexagon*.xml\n+F: docs/system/target-hexagon.rst\n+F: docs/system/hexagon/cdsp.rst\n+F: docs/devel/hexagon-sys.rst\n T: git https://github.com/quic/qemu.git hex-next\n \n Hexagon idef-parser\ndiff --git a/docs/devel/hexagon-sys.rst b/docs/devel/hexagon-sys.rst\nnew file mode 100644\nindex 00000000000..92ebc32dce8\n--- /dev/null\n+++ b/docs/devel/hexagon-sys.rst\n@@ -0,0 +1,112 @@\n+.. SPDX-License-Identifier: GPL-2.0-or-later\n+\n+.. _Hexagon-System-arch:\n+\n+Hexagon System Architecture\n+===========================\n+\n+The hexagon architecture has some unique elements which are described here.\n+\n+Interrupts\n+----------\n+When interrupts arrive at a Hexagon DSP core, they are priority-steered to\n+be handled by an eligible hardware thread with the lowest priority.\n+\n+Memory\n+------\n+Each hardware thread has an ``SSR.ASID`` field that contains its Address\n+Space Identifier. This value is catenated with a 32-bit virtual address -\n+the MMU can then resolve this extended virtual address to a physical address.\n+\n+TLBs\n+----\n+The format of a TLB entry is shown below.\n+\n+.. note::\n+ The Small Core DSPs have a different TLB format which is not yet\n+ supported.\n+\n+.. admonition:: Diagram\n+\n+ .. code:: text\n+\n+ 6 5 4 3\n+ 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ |v|g|x|A|A| | |\n+ |a|l|P|1|0| ASID | Virtual Page |\n+ |l|b| | | | | |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+\n+ 3 2 1 0\n+ 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+ | | | | | | | |\n+ |x|w|r|u|Cacheab| Physical Page |S|\n+ | | | | | | | |\n+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+\n+\n+\n+* ASID: the address-space identifier\n+* A1, A0: the behavior of these cache line attributes are not modeled by QEMU.\n+* xP: the extra-physical bit is the most significant physical address bit.\n+* S: the S bit and the LSBs of the physical page indicate the page size\n+* val: this is the 'valid' bit, when set it indicates that page matching\n+ should consider this entry.\n+\n+.. list-table:: Page sizes\n+ :widths: 25 25 50\n+ :header-rows: 1\n+\n+ * - S-bit\n+ - Phys page LSBs\n+ - Page size\n+ * - 1\n+ - N/A\n+ - 4kb\n+ * - 0\n+ - 0b1\n+ - 16kb\n+ * - 0\n+ - 0b10\n+ - 64kb\n+ * - 0\n+ - 0b100\n+ - 256kb\n+ * - 0\n+ - 0b1000\n+ - 1MB\n+ * - 0\n+ - 0b10000\n+ - 4MB\n+ * - 0\n+ - 0b100000\n+ - 16MB\n+\n+* glb: if the global bit is set, the ASID is not considered when matching\n+ TLBs.\n+* Cacheab: the cacheability attributes of TLBs are not modeled, these bits\n+ are ignored.\n+* RWX: read-, write-, execute-, enable bits. Indicates if user programs\n+ are permitted to read/write/execute the given page.\n+* U: indicates if user programs can access this page.\n+\n+Scheduler\n+---------\n+The Hexagon system architecture has a feature to assist the guest OS\n+task scheduler. The guest OS can enable this feature by setting\n+``SCHEDCFG.EN``. The ``BESTWAIT`` register is programmed by the guest OS\n+to indicate the priority of the highest priority task waiting to run on a\n+hardware thread. The reschedule interrupt is triggered when any hardware\n+thread's priority in ``STID.PRIO`` is worse than the ``BESTWAIT``. When\n+it is triggered, the ``BESTWAIT.PRIO`` value is reset to 0x1ff.\n+\n+HVX Coprocessor\n+---------------\n+The Supervisor Status Register field ``SSR.XA`` binds a DSP hardware thread\n+to one of the eight possible HVX contexts. The guest OS is responsible for\n+managing this resource.\n+\n+.. seealso::\n+\n+ ``target/hexagon/README`` in the QEMU source tree for more info about Hexagon.\ndiff --git a/docs/devel/index-internals.rst b/docs/devel/index-internals.rst\nindex 7a0678cbdd3..0471db80645 100644\n--- a/docs/devel/index-internals.rst\n+++ b/docs/devel/index-internals.rst\n@@ -14,6 +14,7 @@ Details about QEMU's various subsystems including how to add features to them.\n block-coroutine-wrapper\n clocks\n ebpf_rss\n+ hexagon-sys\n migration/index\n multi-process\n reset\ndiff --git a/docs/system/hexagon/cdsp.rst b/docs/system/hexagon/cdsp.rst\nnew file mode 100644\nindex 00000000000..237529273cb\n--- /dev/null\n+++ b/docs/system/hexagon/cdsp.rst\n@@ -0,0 +1,12 @@\n+.. SPDX-License-Identifier: GPL-2.0-or-later\n+\n+Compute DSP\n+===========\n+\n+A Hexagon CDSP is designed as a computation offload device for an SoC. The\n+``V66G_1024`` machine contains:\n+\n+* L2VIC interrupt controller\n+* QTimer timer device\n+\n+This machine will support any Hexagon CPU, but will default to ``v66``.\ndiff --git a/docs/system/target-hexagon.rst b/docs/system/target-hexagon.rst\nnew file mode 100644\nindex 00000000000..5f7084a6a08\n--- /dev/null\n+++ b/docs/system/target-hexagon.rst\n@@ -0,0 +1,102 @@\n+.. SPDX-License-Identifier: GPL-2.0-or-later\n+\n+.. _Hexagon-System-emulator:\n+\n+Hexagon System emulator\n+-----------------------\n+\n+Use the ``qemu-system-hexagon`` executable to simulate a 32-bit Hexagon\n+machine.\n+\n+Hexagon Machines\n+================\n+\n+Hexagon DSPs are suited to various functions and generally appear in a\n+\"DSP subsystem\" of a larger system-on-chip (SoC).\n+\n+Hexagon DSPs are often included in a subsystem that looks like the diagram\n+below. Instructions are loaded into DDR before the DSP is brought out of\n+reset and the first instructions are fetched from DDR via the EVB/reset vector.\n+\n+In a real system, a TBU/SMMU would normally arbitrate AXI accesses but\n+we don't have a need to model that for QEMU.\n+\n+Hexagon DSP cores use simultaneous multithreading (SMT) with as many as 8\n+hardware threads.\n+\n+.. admonition:: Diagram\n+\n+ .. code:: text\n+\n+ AHB (local) bus AXI (global) bus\n+ │ │\n+ │ │\n+ ┌─────────┐ │ ┌─────────────────┐ │\n+ │ L2VIC ├──┤ │ │ │\n+ │ ├──┼───────► ├───────┤\n+ └─────▲───┘ │ │ Hexagon DSP │ │\n+ │ │ │ │ │ ┌─────┐\n+ │ │ │ N threads │ │ │ DDR │\n+ │ ├───────┤ │ │ │ │\n+ ┌────┴──┐ │ │ │ ├────────┤ │\n+ │QTimer ├───┤ │ │ │ │ │\n+ │ │ │ │ │ │ │ │\n+ └───────┘ │ │ ┌─────────┐ │ │ │ │\n+ │ │ ┌─────────┐│ │ │ │ │\n+ ┌───────┐ │ │ │ HVX xM ││ │ │ │ │\n+ │QDSP6SS├───┤ │ │ │┘ │ │ │ │\n+ └───────┘ │ │ └─────────┘ │ │ └─────┘\n+ │ │ │ │\n+ ┌───────┐ │ └─────────────────┘ │\n+ │ CSR ├───┤\n+ └───────┘ │ ┌──────┐ ┌───────────┐\n+ │ │ TCM │ │ VTCM │\n+ │ │ │ │\n+ └──────┘ │ │\n+ │ │\n+ │ │\n+ │ │\n+ └───────────┘\n+\n+Components\n+----------\n+Other than l2vic and HVX, the components below are not implemented in QEMU.\n+\n+* L2VIC: the L2 vectored interrupt controller. Supports 1024 input\n+ interrupts, edge- or level-triggered. The core ISA has system registers\n+ ``VID``, ``VID1`` which read through to the L2VIC device.\n+* QTimer: ARMSSE-based programmable timer device. Its interrupts are\n+ wired to the L2VIC. System registers ``TIMER``, ``UTIMER`` read\n+ through to the QTimer device.\n+* QDSP6SS: DSP subsystem features, accessible to the entire SoC, including\n+ DSP NMI, watchdog, reset, etc.\n+* CSR: Configuration/Status Registers.\n+* TCM: DSP-exclusive tightly-coupled memory. This memory can be used for\n+ DSPs when isolated from DDR and in some bootstrapping modes.\n+* VTCM: DSP-exclusive vector tightly-coupled memory. This memory is accessed\n+ by some HVX instructions.\n+* HVX: the vector coprocessor supports 64 and 128-byte vector registers.\n+ 64-byte mode is not implemented in QEMU.\n+\n+\n+Bootstrapping\n+-------------\n+Hexagon systems do not generally have access to a block device. So, for\n+QEMU the typical use case involves loading a binary or ELF file into memory\n+and executing from the indicated start address::\n+\n+ $ qemu-system-hexagon -kernel ./prog -append 'arg1 arg2'\n+\n+Semihosting\n+-----------\n+Hexagon supports a semihosting interface similar to other architectures'.\n+The ``trap0`` instruction can activate these semihosting calls so that the\n+guest software can access the host console and filesystem. Semihosting\n+is not yet implemented in QEMU hexagon.\n+\n+\n+Hexagon Features\n+================\n+.. toctree::\n+ hexagon/cdsp\n+\ndiff --git a/docs/system/targets.rst b/docs/system/targets.rst\nindex 5b12858b216..5ebdd0f7fea 100644\n--- a/docs/system/targets.rst\n+++ b/docs/system/targets.rst\n@@ -30,3 +30,4 @@ Contents:\n target-sparc64\n target-i386\n target-xtensa\n+ target-hexagon\n", "prefixes": [ "v3", "01/37" ] }