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GET /api/patches/2202546/?format=api
{ "id": 2202546, "url": "http://patchwork.ozlabs.org/api/patches/2202546/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-19-brian.cain@oss.qualcomm.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260227203627.932864-19-brian.cain@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-27T20:36:08", "name": "[v3,18/37] target/hexagon: Add handlers for guest/sysreg r/w", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b7fbda795136f165646db7a84821479168af9044", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260227203627.932864-19-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 493813, "url": "http://patchwork.ozlabs.org/api/series/493813/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=493813", "date": "2026-02-27T20:35:57", "name": "Hexagon system emulation - Part 1/3", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/493813/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2202546/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2202546/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=QhDPUjoX;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=jrpkBeBb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-16", "X-Spam_score": "-1.7", "X-Spam_bar": "-", "X-Spam_report": "(-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.706,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.401, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nThis commit provides handlers to generate TCG for guest and system\nregister reads and writes. They will be leveraged by a future commit.\n\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/genptr.c | 147 ++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 147 insertions(+)", "diff": "diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c\nindex 9eb21da6f3e..908f7e5e2e5 100644\n--- a/target/hexagon/genptr.c\n+++ b/target/hexagon/genptr.c\n@@ -23,6 +23,7 @@\n #include \"exec/helper-gen.h\"\n #include \"insn.h\"\n #include \"opcodes.h\"\n+#include \"sys_macros.h\"\n #include \"translate.h\"\n #define QEMU_GENERATE /* Used internally by macros.h */\n #include \"macros.h\"\n@@ -120,6 +121,152 @@ TCGv get_result_pred(DisasContext *ctx, int pnum)\n }\n }\n \n+#ifndef CONFIG_USER_ONLY\n+G_GNUC_UNUSED\n+static bool greg_writable(int rnum, bool pair)\n+{\n+ if (pair) {\n+ if (rnum < HEX_GREG_G3) {\n+ return true;\n+ }\n+ qemu_log_mask(LOG_UNIMP,\n+ \"Warning: ignoring write to guest register pair G%d:%d\\n\",\n+ rnum + 1, rnum);\n+ } else {\n+ if (rnum <= HEX_GREG_G3) {\n+ return true;\n+ }\n+ qemu_log_mask(LOG_UNIMP,\n+ \"Warning: ignoring write to guest register G%d\\n\", rnum);\n+ }\n+ return false;\n+}\n+\n+G_GNUC_UNUSED\n+static void check_greg_impl(int rnum, bool pair)\n+{\n+ if (pair && (!greg_implemented(rnum) || !greg_implemented(rnum + 1))) {\n+ qemu_log_mask(LOG_UNIMP,\n+ \"Warning: guest register pair G%d:%d is unimplemented or \"\n+ \"reserved. Read will yield 0.\\n\",\n+ rnum + 1, rnum);\n+ } else if (!pair && !greg_implemented(rnum)) {\n+ qemu_log_mask(LOG_UNIMP,\n+ \"Warning: guest register G%d is unimplemented or reserved.\"\n+ \" Read will yield 0.\\n\", rnum);\n+ }\n+}\n+\n+G_GNUC_UNUSED\n+static inline void gen_log_greg_write(DisasContext *ctx, int rnum, TCGv val)\n+{\n+ tcg_gen_mov_tl(ctx->greg_new_value[rnum], val);\n+}\n+\n+G_GNUC_UNUSED\n+static void gen_log_greg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 val)\n+{\n+ TCGv val32 = tcg_temp_new();\n+\n+ /* Low word */\n+ tcg_gen_extrl_i64_i32(val32, val);\n+ gen_log_greg_write(ctx, rnum, val32);\n+\n+ /* High word */\n+ tcg_gen_extrh_i64_i32(val32, val);\n+ gen_log_greg_write(ctx, rnum + 1, val32);\n+}\n+\n+static const target_ulong sreg_immut_masks[NUM_SREGS] = {\n+ [HEX_SREG_STID] = 0xff00ff00,\n+ [HEX_SREG_ELR] = 0x00000003,\n+ [HEX_SREG_SSR] = 0x00008000,\n+ [HEX_SREG_CCR] = 0x10e0ff24,\n+ [HEX_SREG_HTID] = IMMUTABLE,\n+ [HEX_SREG_IMASK] = 0xffff0000,\n+ [HEX_SREG_GEVB] = 0x000000ff,\n+};\n+\n+G_GNUC_UNUSED\n+static void gen_log_sreg_write(DisasContext *ctx, int rnum, TCGv val)\n+{\n+ const target_ulong reg_mask = sreg_immut_masks[rnum];\n+\n+ if (reg_mask != IMMUTABLE) {\n+ if (rnum < HEX_SREG_GLB_START) {\n+ gen_masked_reg_write(val, hex_t_sreg[rnum], reg_mask);\n+ tcg_gen_mov_tl(ctx->t_sreg_new_value[rnum], val);\n+ } else {\n+ gen_helper_sreg_write_masked(tcg_env, tcg_constant_i32(rnum), val);\n+ }\n+ }\n+}\n+\n+G_GNUC_UNUSED\n+static void gen_log_sreg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 val)\n+{\n+ TCGv val32 = tcg_temp_new();\n+\n+ /* Low word */\n+ tcg_gen_extrl_i64_i32(val32, val);\n+ gen_log_sreg_write(ctx, rnum, val32);\n+\n+ /* High word */\n+ tcg_gen_extrh_i64_i32(val32, val);\n+ gen_log_sreg_write(ctx, rnum + 1, val32);\n+}\n+\n+G_GNUC_UNUSED\n+static void gen_read_sreg(TCGv dst, int reg_num)\n+{\n+ if (reg_num >= HEX_SREG_GLB_START || reg_num == HEX_SREG_BADVA) {\n+ gen_helper_sreg_read(dst, tcg_env, tcg_constant_i32(reg_num));\n+ } else {\n+ tcg_gen_mov_tl(dst, hex_t_sreg[reg_num]);\n+ }\n+}\n+\n+G_GNUC_UNUSED\n+static void gen_read_sreg_pair(TCGv_i64 dst, int reg_num)\n+{\n+ if (reg_num < HEX_SREG_GLB_START) {\n+ if (reg_num + 1 == HEX_SREG_BADVA) {\n+ TCGv badva = tcg_temp_new();\n+ gen_helper_sreg_read(badva, tcg_env,\n+ tcg_constant_tl(HEX_SREG_BADVA));\n+ tcg_gen_concat_i32_i64(dst, hex_t_sreg[reg_num], badva);\n+ } else {\n+ tcg_gen_concat_i32_i64(dst, hex_t_sreg[reg_num],\n+ hex_t_sreg[reg_num + 1]);\n+ }\n+ } else {\n+ gen_helper_sreg_read_pair(dst, tcg_env, tcg_constant_tl(reg_num));\n+ }\n+}\n+\n+G_GNUC_UNUSED\n+static void gen_read_greg(TCGv dst, int reg_num)\n+{\n+ if (reg_num <= HEX_GREG_G3) {\n+ tcg_gen_mov_tl(dst, hex_greg[reg_num]);\n+ } else {\n+ gen_helper_greg_read(dst, tcg_env, tcg_constant_tl(reg_num));\n+ }\n+}\n+\n+G_GNUC_UNUSED\n+static void gen_read_greg_pair(TCGv_i64 dst, int reg_num)\n+{\n+ if (reg_num == HEX_GREG_G0 || reg_num == HEX_GREG_G2) {\n+ tcg_gen_concat_i32_i64(dst, hex_greg[reg_num],\n+ hex_greg[reg_num + 1]);\n+ } else {\n+ gen_helper_greg_read_pair(dst, tcg_env, tcg_constant_tl(reg_num));\n+ }\n+}\n+#endif\n+\n+\n void gen_pred_write(DisasContext *ctx, int pnum, TCGv val)\n {\n TCGv pred = get_result_pred(ctx, pnum);\n", "prefixes": [ "v3", "18/37" ] }