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GET /api/patches/2200196/?format=api
{ "id": 2200196, "url": "http://patchwork.ozlabs.org/api/patches/2200196/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260224111044.3487873-6-mika.westerberg@linux.intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260224111044.3487873-6-mika.westerberg@linux.intel.com>", "list_archive_url": null, "date": "2026-02-24T11:10:44", "name": "[5/5] PCI/PTM: Do not enable PTM automatically for Root and Switch Upstream Ports", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "1cfba5b38a6ffe13a426e8f730c6f54b4280808a", "submitter": { "id": 14534, "url": "http://patchwork.ozlabs.org/api/people/14534/?format=api", "name": "Mika Westerberg", "email": "mika.westerberg@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260224111044.3487873-6-mika.westerberg@linux.intel.com/mbox/", "series": [ { "id": 493142, "url": "http://patchwork.ozlabs.org/api/series/493142/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=493142", "date": "2026-02-24T11:10:41", "name": "PCI / igc: Improvements related to PTM enabling", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/493142/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2200196/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2200196/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=oOVWotfc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.137; 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envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=<UNKNOWN> ", "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 smtp4.osuosl.org 7DAB841C03", "OpenDKIM Filter v2.11.0 smtp4.osuosl.org 745CB41BFE" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org;\n\ts=default; t=1771931459;\n\tbh=l7p5UPPOSrNDIxlBHSX4/hAAd/Wjzwd/FOq7KnYJIrA=;\n\th=From:To:Cc:Date:In-Reply-To:References:Subject:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=oOVWotfcsn6/xa0Cq7flCN8VmUnD6W41o9QXkcfGkVG/FzMbJD2sdFQNYtbApCn+3\n\t M+/2pWtVEET5xyf6KiKBdkJmmpXFcDP8Z/o5GmO3YsuahmGeZhtdPpzhg6ajB4Cst0\n\t mvgo/GAs6Veyen37JeA+pniFAi5g45P3WLmJ5OIyD6B+y/1yDC3HIuSkB9FFCl+i9/\n\t qJ1oAlpVd8qbuZ1aeWla3C987E54hQ0MQyALkb8Je0gSgbRqPwvQMF5433kcKSahpj\n\t dzwXf4vsuAB2XYkO1Th2GU2grbgjZefpvUDqWvg+4RT8Q4xHdqY3Th67SbZtUymYR9\n\t rS0b2neJhL1UQ==", "Received-SPF": "Pass (mailfrom) identity=mailfrom; client-ip=192.198.163.19;\n helo=mgamail.intel.com; envelope-from=mika.westerberg@linux.intel.com;\n receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp4.osuosl.org 745CB41BFE", "X-CSE-ConnectionGUID": [ "K6uoOOXJTfqKdVQZc9d6Ag==", "s1nPANqzQyykN4lynBSZJA==" ], "X-CSE-MsgGUID": [ "5IJqYomdSuii62izf0AQ3A==", "jVhs4F/jSFK92aVLDpzhPg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11710\"; a=\"71974283\"", "E=Sophos;i=\"6.21,308,1763452800\"; d=\"scan'208\";a=\"71974283\"", "E=Sophos;i=\"6.21,308,1763452800\"; d=\"scan'208\";a=\"216037820\"" ], "X-ExtLoop1": "1", "From": "Mika Westerberg <mika.westerberg@linux.intel.com>", "To": "linux-pci@vger.kernel.org", "Cc": "intel-wired-lan@lists.osuosl.org, Bjorn Helgaas <bhelgaas@google.com>,\n Lukas Wunner <lukas@wunner.de>, Tony Nguyen <anthony.l.nguyen@intel.com>,\n Przemek Kitszel <przemyslaw.kitszel@intel.com>,\n Andrew Lunn <andrew+netdev@lunn.ch>,\n \"David S . Miller\" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>,\n Paolo Abeni <pabeni@redhat.com>, Saeed Mahameed <saeedm@nvidia.com>,\n Leon Romanovsky <leon@kernel.org>, Tariq Toukan <tariqt@nvidia.com>,\n Mark Bloch <mbloch@nvidia.com>, Richard Cochran <richardcochran@gmail.com>,\n Andy Shevchenko <andriy.shevchenko@intel.com>,\n Vitaly Lifshits <vitaly.lifshits@intel.com>,\n =?utf-8?q?Ilpo_J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>,\n Vinicius Costa Gomes <vinicius.gomes@intel.com>,\n Dima Ruinskiy <dima.ruinskiy@intel.com>,\n Mika Westerberg <mika.westerberg@linux.intel.com>", "Date": "Tue, 24 Feb 2026 12:10:44 +0100", "Message-ID": "<20260224111044.3487873-6-mika.westerberg@linux.intel.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260224111044.3487873-1-mika.westerberg@linux.intel.com>", "References": "<20260224111044.3487873-1-mika.westerberg@linux.intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1771931455; x=1803467455;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Nx43f3p0wM+lMNlN3Kkqeor3DPzX52qzSrgORMn8EsU=;\n b=nfPJ64NaequjHTuGGQltkN6V0IUFrj1Zj7xhePkduRCXNDszlJJVpj6q\n VBPY3xKef0KywQhNsA4wn9W4rBuaPUMln+hSe2QM0VR6YqTxTMQ3pVPuG\n mab398eE0mAXp/x5AvP+rUgrUCt50Wc8Rx5YWaZZhraVhvaSVQQGFme2T\n B5oCh+Ze6RCOZ16hd72jOV/zSNC7vfpyeDykLsQQ5TQ0cFbZmWmD9RhB9\n V45AaD9a+y3lK053Z+lGxwifh2Wk/mJmT2F0uUXk3mLDFgP4bw/5z2wGS\n ugCUcqfcQMmRQn/3inJmy1/0dUctJG+wuCrsi+0mrhfqO2V6M2pjJgeNF\n w==;", "X-Mailman-Original-Authentication-Results": [ "smtp4.osuosl.org;\n dmarc=none (p=none dis=none)\n header.from=linux.intel.com", "smtp4.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=nfPJ64Na" ], "Subject": "[Intel-wired-lan] [PATCH 5/5] PCI/PTM: Do not enable PTM\n automatically for Root and Switch Upstream Ports", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Currently we enable PTM automatically for Root and Switch Upstream Ports\nif the advertised capabilities support the relevant role. However, there\nare few issues with this. First of all if there is no Endpoint that\nactually needs the PTM functionality, this is just wasting link\nbandwidth. There are just a couple of drivers calling pci_ptm_enable()\nin the tree.\n\nSecondly we do the enablement in pci_ptm_init() that is called pretty\nearly for the Switch Upstream Port before Downstream Ports are even\nenumerated. Since the Upstream Port configuration affects the whole\nSwitch enabling it this early might cause the PTM requests to be sent\nalready. We actually do see effect of this:\n\n pcieport 0000:00:07.1: pciehp: Slot(6-1): Card present\n pcieport 0000:00:07.1: pciehp: Slot(6-1): Link Up\n pci 0000:2c:00.0: [8086:5786] type 01 class 0x060400 PCIe Switch Upstream Port\n pci 0000:2c:00.0: PCI bridge to [bus 00]\n pci 0000:2c:00.0: bridge window [io 0x0000-0x0fff]\n pci 0000:2c:00.0: bridge window [mem 0x00000000-0x000fffff]\n pci 0000:2c:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref]\n ...\n pci 0000:2c:00.0: PME# supported from D0 D1 D2 D3hot D3cold\n pci 0000:2c:00.0: PTM enabled, 4ns granularity\n\nAt this point we have only enumerated the Switch Upstream Port and now\nPTM got enabled which immediately triggers flood of these:\n\n pcieport 0000:00:07.1: AER: Multiple Uncorrectable (Non-Fatal) error message received from 0000:00:07.1\n pcieport 0000:00:07.1: PCIe Bus Error: severity=Uncorrectable (Non-Fatal), type=Transaction Layer, (Receiver ID)\n pcieport 0000:00:07.1: device [8086:d44f] error status/mask=00200000/00000000\n pcieport 0000:00:07.1: [21] ACSViol (First)\n pcieport 0000:00:07.1: AER: TLP Header: 0x34000000 0x00000052 0x00000000 0x00000000\n pcieport 0000:00:07.1: AER: device recovery successful\n pcieport 0000:00:07.1: AER: Uncorrectable (Non-Fatal) error message received from 0000:00:07.1\n\nIn the above TLP Header the Requester ID is 0 which rightfully triggers\nan error as we have ACS Source Validation enabled.\n\nFor this reason change the PTM enablement to happen at the time\npci_enable_ptm() is called. It will try to enable PTM first for upstream\ndevices before enabling for the Endpoint itself. For disable path we\nneed to keep count of how many times PTM has been enabled and disable\nonly on the last so change the dev->ptm_enabled to a counter (and rename\nit to dev->ptm_enable_cnt analogous to dev->pci_enable_cnt).\n\nSigned-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>\n---\n drivers/pci/pcie/ptm.c | 68 ++++++++++++++++++++++++------------------\n include/linux/pci.h | 2 +-\n 2 files changed, 40 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c\nindex 2c848ae4f15f..a41ffd1914de 100644\n--- a/drivers/pci/pcie/ptm.c\n+++ b/drivers/pci/pcie/ptm.c\n@@ -52,6 +52,7 @@ void pci_ptm_init(struct pci_dev *dev)\n \t\treturn;\n \n \tdev->ptm_cap = ptm;\n+\tatomic_set(&dev->ptm_enable_cnt, 0);\n \tpci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u32));\n \n \tpci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap);\n@@ -85,10 +86,6 @@ void pci_ptm_init(struct pci_dev *dev)\n \t\tdev->ptm_responder = 1;\n \tif (cap & PCI_PTM_CAP_REQ)\n \t\tdev->ptm_requester = 1;\n-\n-\tif (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||\n-\t pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM)\n-\t\tpci_enable_ptm(dev);\n }\n \n void pci_save_ptm_state(struct pci_dev *dev)\n@@ -129,26 +126,11 @@ void pci_restore_ptm_state(struct pci_dev *dev)\n static int __pci_enable_ptm(struct pci_dev *dev)\n {\n \tu16 ptm = dev->ptm_cap;\n-\tstruct pci_dev *ups;\n \tu32 ctrl;\n \n \tif (!ptm)\n \t\treturn -EINVAL;\n \n-\t/*\n-\t * A device uses local PTM Messages to request time information\n-\t * from a PTM Root that's farther upstream. Every device along the\n-\t * path must support PTM and have it enabled so it can handle the\n-\t * messages. Therefore, if this device is not a PTM Root, the\n-\t * upstream link partner must have PTM enabled before we can enable\n-\t * PTM.\n-\t */\n-\tif (!dev->ptm_root) {\n-\t\tups = pci_upstream_ptm(dev);\n-\t\tif (!ups || !ups->ptm_enabled)\n-\t\t\treturn -EINVAL;\n-\t}\n-\n \tswitch (pci_pcie_type(dev)) {\n \tcase PCI_EXP_TYPE_ROOT_PORT:\n \t\tif (!dev->ptm_root)\n@@ -193,11 +175,35 @@ int pci_enable_ptm(struct pci_dev *dev)\n \tint rc;\n \tchar clock_desc[8];\n \n+\t/*\n+\t * A device uses local PTM Messages to request time information\n+\t * from a PTM Root that's farther upstream. Every device along\n+\t * the path must support PTM and have it enabled so it can\n+\t * handle the messages. Therefore, if this device is not a PTM\n+\t * Root, the upstream link partner must have PTM enabled before\n+\t * we can enable PTM.\n+\t */\n+\tif (!dev->ptm_root) {\n+\t\tstruct pci_dev *parent;\n+\n+\t\tparent = pci_upstream_ptm(dev);\n+\t\tif (!parent)\n+\t\t\treturn -EINVAL;\n+\t\t/* Enable PTM for the parent */\n+\t\trc = pci_enable_ptm(parent);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\t/* Already enabled? */\n+\tif (atomic_inc_return(&dev->ptm_enable_cnt) > 1)\n+\t\treturn 0;\n+\n \trc = __pci_enable_ptm(dev);\n-\tif (rc)\n+\tif (rc) {\n+\t\tatomic_dec(&dev->ptm_enable_cnt);\n \t\treturn rc;\n-\n-\tdev->ptm_enabled = 1;\n+\t}\n \n \tswitch (dev->ptm_granularity) {\n \tcase 0:\n@@ -239,27 +245,31 @@ static void __pci_disable_ptm(struct pci_dev *dev)\n */\n void pci_disable_ptm(struct pci_dev *dev)\n {\n-\tif (dev->ptm_enabled) {\n+\tstruct pci_dev *parent;\n+\n+\tif (atomic_dec_and_test(&dev->ptm_enable_cnt))\n \t\t__pci_disable_ptm(dev);\n-\t\tdev->ptm_enabled = 0;\n-\t}\n+\n+\tparent = pci_upstream_ptm(dev);\n+\tif (parent)\n+\t\tpci_disable_ptm(parent);\n }\n EXPORT_SYMBOL(pci_disable_ptm);\n \n /*\n- * Disable PTM, but preserve dev->ptm_enabled so we silently re-enable it on\n+ * Disable PTM, but preserve dev->ptm_enable_cnt so we silently re-enable it on\n * resume if necessary.\n */\n void pci_suspend_ptm(struct pci_dev *dev)\n {\n-\tif (dev->ptm_enabled)\n+\tif (atomic_read(&dev->ptm_enable_cnt))\n \t\t__pci_disable_ptm(dev);\n }\n \n /* If PTM was enabled before suspend, re-enable it when resuming */\n void pci_resume_ptm(struct pci_dev *dev)\n {\n-\tif (dev->ptm_enabled)\n+\tif (atomic_read(&dev->ptm_enable_cnt))\n \t\t__pci_enable_ptm(dev);\n }\n \n@@ -268,7 +278,7 @@ bool pcie_ptm_enabled(struct pci_dev *dev)\n \tif (!dev)\n \t\treturn false;\n \n-\treturn dev->ptm_enabled;\n+\treturn atomic_read(&dev->ptm_enable_cnt);\n }\n EXPORT_SYMBOL(pcie_ptm_enabled);\n \ndiff --git a/include/linux/pci.h b/include/linux/pci.h\nindex 8aaa72dcb164..7e49d35d81a5 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -518,7 +518,7 @@ struct pci_dev {\n \tunsigned int\tptm_root:1;\n \tunsigned int\tptm_responder:1;\n \tunsigned int\tptm_requester:1;\n-\tunsigned int\tptm_enabled:1;\n+\tatomic_t\tptm_enable_cnt;\t\t/* pci_enable_ptm() has been called */\n \tu8\t\tptm_granularity;\n #endif\n #ifdef CONFIG_PCI_MSI\n", "prefixes": [ "5/5" ] }