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GET /api/patches/2197406/?format=api
{ "id": 2197406, "url": "http://patchwork.ozlabs.org/api/patches/2197406/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217212707.2450423-17-cassel@kernel.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217212707.2450423-17-cassel@kernel.org>", "list_archive_url": null, "date": "2026-02-17T21:27:12", "name": "[6/9] PCI: dwc: Disable BARs in common code instead of in each glue driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8ae1df8d6d570403ae66612202e6d2cd29f8d8f1", "submitter": { "id": 87751, "url": "http://patchwork.ozlabs.org/api/people/87751/?format=api", "name": "Niklas Cassel", "email": "cassel@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217212707.2450423-17-cassel@kernel.org/mbox/", "series": [ { "id": 492482, "url": "http://patchwork.ozlabs.org/api/series/492482/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492482", "date": "2026-02-17T21:27:06", "name": "PCI: endpoint differentiate between disabled and reserved BARs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492482/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197406/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197406/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47513-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=mwp4osZS;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-47513-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"mwp4osZS\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fFt6x1YqMz1xpl\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 18 Feb 2026 08:28:41 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id D7C27302AD0B\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 17 Feb 2026 21:28:12 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id AD20C2F617F;\n\tTue, 17 Feb 2026 21:28:11 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 87EE828C006;\n\tTue, 17 Feb 2026 21:28:11 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id BC7D4C4CEF7;\n\tTue, 17 Feb 2026 21:28:02 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1771363691; cv=none;\n b=ULXJBVTFcuZPW7iUdJ3OjS87+ISLiacwtH1/FagwtgnY1YxFtuQE4tStYObrXOAFJo0Kj3iiFvAa3xoxXmzRBeHXC382qeld7ynL3MgdnohAuVO35E286TOxCFt5W3DzewMWuoqpQrSmaVVa96Ewcl3PaH5bekaku8H5wjGq4rI=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1771363691; c=relaxed/simple;\n\tbh=e013MclqvhWFmfVVjQRnVhkHXJ5Zt6PgZko858Ti8vQ=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=eoS7t/BNlK2gUk88qHhr9jww1urhxPyPJ5+KLuKu4IVGp/92es4mah+f691xPsoSBuWpDvFHZ8n3iwmXgNWr6pB+yAip/Xwj6wRgg5zxGIrPmxBpdzFNpN6al1tYije3SF7nVNd64FOdCeCj/ALBq9FjphsEpWJNRRfLN0ln8gk=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=mwp4osZS; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1771363691;\n\tbh=e013MclqvhWFmfVVjQRnVhkHXJ5Zt6PgZko858Ti8vQ=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=mwp4osZSI+dyTPIohQo8kJBRdtoYQCOyPv9CBGBHyLCZa80LnZrSQOtLQgSD4GUWm\n\t KvwDCw9UWiOjJvq5p2OquibLfYY6InXuBNzyehizELzJVXCCXLhydYWyB/pvyQ/HJ3\n\t /s6XVNzGFbXQjWHBYx7C3s8K4QFAhpHvO1CVmk5OBPZOTjGs0RLP3lCwKksP4WNIMu\n\t atjTPMTT0zqVOKGNOshR1dnZwR49LkaxWmbbS8F2IeVhj7uOFS+1FwKYOFbBXEnxOy\n\t AC2e/BFm4w/l0hja71Y1lCIdqlQeSqgV1UFO8KTz7rRcVb86ACu89QVJjxWVBtldrE\n\t UdIOV7yurKFsg==", "From": "Niklas Cassel <cassel@kernel.org>", "To": "Vignesh Raghavendra <vigneshr@ti.com>,\n Siddharth Vadapalli <s-vadapalli@ti.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Richard Zhu <hongxing.zhu@nxp.com>,\n Lucas Stach <l.stach@pengutronix.de>, Frank Li <Frank.Li@nxp.com>,\n Sascha Hauer <s.hauer@pengutronix.de>,\n Pengutronix Kernel Team <kernel@pengutronix.de>,\n Fabio Estevam <festevam@gmail.com>, Minghuan Lian <minghuan.Lian@nxp.com>,\n Mingkai Hu <mingkai.hu@nxp.com>, Roy Zang <roy.zang@nxp.com>,\n Jesper Nilsson <jesper.nilsson@axis.com>, Jingoo Han <jingoohan1@gmail.com>,\n Heiko Stuebner <heiko@sntech.de>,\n Marek Vasut <marek.vasut+renesas@gmail.com>,\n Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,\n Geert Uytterhoeven <geert+renesas@glider.be>,\n Magnus Damm <magnus.damm@gmail.com>,\n Christian Bruel <christian.bruel@foss.st.com>,\n Maxime Coquelin <mcoquelin.stm32@gmail.com>,\n Alexandre Torgue <alexandre.torgue@foss.st.com>,\n Thierry Reding <thierry.reding@gmail.com>,\n Jonathan Hunter <jonathanh@nvidia.com>,\n Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n Masami Hiramatsu <mhiramat@kernel.org>", "Cc": "Manikanta Maddireddy <mmaddireddy@nvidia.com>,\n\tKoichiro Den <den@valinux.co.jp>,\n\tDamien Le Moal <dlemoal@kernel.org>,\n\tNiklas Cassel <cassel@kernel.org>,\n\tlinux-omap@vger.kernel.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\timx@lists.linux.dev,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tlinux-arm-kernel@axis.com,\n\tlinux-rockchip@lists.infradead.org,\n\tlinux-arm-msm@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org,\n\tlinux-stm32@st-md-mailman.stormreply.com,\n\tlinux-tegra@vger.kernel.org", "Subject": "[PATCH 6/9] PCI: dwc: Disable BARs in common code instead of in each\n glue driver", "Date": "Tue, 17 Feb 2026 22:27:12 +0100", "Message-ID": "<20260217212707.2450423-17-cassel@kernel.org>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260217212707.2450423-11-cassel@kernel.org>", "References": "<20260217212707.2450423-11-cassel@kernel.org>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=13258; i=cassel@kernel.org;\n h=from:subject; bh=e013MclqvhWFmfVVjQRnVhkHXJ5Zt6PgZko858Ti8vQ=;\n b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGDKn3DUQmNtokbd6C9eDh8FdTRIir7pTFiwI4hFrn713w\n /Vk56lWHaUsDGJcDLJiiiy+P1z2F3e7TzmueMcGZg4rE8gQBi5OAZhI+W6G/+W3nW+JRfZ+jGQv\n m5lqwirCdsSQp/biUnkHjtAuXoaQUEaGn+G9sWmZpcePrQtT6Z5qs2zL2k0NfTLTp74JkNuxb34\n KCwA=", "X-Developer-Key": "i=cassel@kernel.org; a=openpgp;\n fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA", "Content-Transfer-Encoding": "8bit" }, "content": "The current EPC core design relies on an EPC driver disabling all BARs by\ndefault. An EPF driver will then enable the BARs that it wants to enabled.\n\nThis design is there because there is no epc->ops->disable_bar().\n(There is a epc->ops->clear_bar(), but that is only to disable a BAR that\nhas been enabled using epc->ops->set_bar() first.)\n\nBy default, an EPF driver will not be able to get/enable BARs that are\nmarked as BAR_RESERVED or BAR_DISABLED (see pci_epc_get_next_free_bar()).\n\nSince the current EPC code design requires an EPC driver to disable all\nBARs by default, let's do this in the DWC common code rather than in each\nglue driver.\n\nBARs that are marked as BAR_RESERVED are not disabled by default.\nThis is because these BARs are hardware backed, and should only be disabled\nexplicitly by an EPF driver if absolutely necessary for the EPF driver to\nfunction correctly. (This is similar to how e.g. NVMe may have vendor\nspecific BARs outside of the mandatory BAR0 which contains the NVMe\nregisters.)\n\nNote that there is currently no EPC operation to disable a BAR that has not\nfirst been programmed using pci_epc_set_bar(). If an EPF driver ever wants\nto disable a BAR marked as BAR_RESERVED, a disable_bar() operation would\nhave to be added first.\n\nNo functional changes intended.\n\nSigned-off-by: Niklas Cassel <cassel@kernel.org>\n---\n drivers/pci/controller/dwc/pci-dra7xx.c | 4 ----\n drivers/pci/controller/dwc/pci-imx6.c | 10 --------\n .../pci/controller/dwc/pci-layerscape-ep.c | 4 ----\n drivers/pci/controller/dwc/pcie-artpec6.c | 4 ----\n .../pci/controller/dwc/pcie-designware-ep.c | 24 +++++++++++++++++++\n .../pci/controller/dwc/pcie-designware-plat.c | 10 --------\n drivers/pci/controller/dwc/pcie-dw-rockchip.c | 4 ----\n drivers/pci/controller/dwc/pcie-qcom-ep.c | 10 --------\n drivers/pci/controller/dwc/pcie-rcar-gen4.c | 10 --------\n drivers/pci/controller/dwc/pcie-stm32-ep.c | 10 --------\n drivers/pci/controller/dwc/pcie-tegra194.c | 10 --------\n drivers/pci/controller/dwc/pcie-uniphier-ep.c | 10 --------\n 12 files changed, 24 insertions(+), 86 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c\nindex d5d26229063f..cd904659c321 100644\n--- a/drivers/pci/controller/dwc/pci-dra7xx.c\n+++ b/drivers/pci/controller/dwc/pci-dra7xx.c\n@@ -378,10 +378,6 @@ static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)\n {\n \tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n \tstruct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);\n-\tenum pci_barno bar;\n-\n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n \n \tdra7xx_pcie_enable_wrapper_interrupts(dra7xx);\n }\ndiff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c\nindex ec1e3557ca53..f5fe5cfc46c7 100644\n--- a/drivers/pci/controller/dwc/pci-imx6.c\n+++ b/drivers/pci/controller/dwc/pci-imx6.c\n@@ -1401,15 +1401,6 @@ static const struct dw_pcie_ops dw_pcie_ops = {\n \t.stop_link = imx_pcie_stop_link,\n };\n \n-static void imx_pcie_ep_init(struct dw_pcie_ep *ep)\n-{\n-\tenum pci_barno bar;\n-\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\n-\tfor (bar = BAR_0; bar <= BAR_5; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-}\n-\n static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,\n \t\t\t\t unsigned int type, u16 interrupt_num)\n {\n@@ -1478,7 +1469,6 @@ imx_pcie_ep_get_features(struct dw_pcie_ep *ep)\n }\n \n static const struct dw_pcie_ep_ops pcie_ep_ops = {\n-\t.init = imx_pcie_ep_init,\n \t.raise_irq = imx_pcie_ep_raise_irq,\n \t.get_features = imx_pcie_ep_get_features,\n };\ndiff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c\nindex 5a03a8f895f9..1f5fccdb4ff4 100644\n--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c\n+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c\n@@ -152,15 +152,11 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)\n \tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n \tstruct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);\n \tstruct dw_pcie_ep_func *ep_func;\n-\tenum pci_barno bar;\n \n \tep_func = dw_pcie_ep_get_func_from_ep(ep, 0);\n \tif (!ep_func)\n \t\treturn;\n \n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-\n \tpcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;\n \tpcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;\n }\ndiff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c\nindex e994b75986c3..55cb957ae1f3 100644\n--- a/drivers/pci/controller/dwc/pcie-artpec6.c\n+++ b/drivers/pci/controller/dwc/pcie-artpec6.c\n@@ -340,15 +340,11 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)\n {\n \tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n \tstruct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);\n-\tenum pci_barno bar;\n \n \tartpec6_pcie_assert_core_reset(artpec6_pcie);\n \tartpec6_pcie_init_phy(artpec6_pcie);\n \tartpec6_pcie_deassert_core_reset(artpec6_pcie);\n \tartpec6_pcie_wait_for_phy(artpec6_pcie);\n-\n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n }\n \n static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,\ndiff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c\nindex 7e7844ff0f7e..5e47517c757c 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c\n@@ -1105,6 +1105,28 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)\n \tdw_pcie_dbi_ro_wr_dis(pci);\n }\n \n+static void dw_pcie_ep_disable_bars(struct dw_pcie_ep *ep)\n+{\n+\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n+\tenum pci_epc_bar_type bar_type;\n+\tenum pci_barno bar;\n+\n+\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {\n+\t\tbar_type = dw_pcie_ep_get_bar_type(ep, bar);\n+\n+\t\t/*\n+\t\t * Reserved BARs should not get disabled by default. All other\n+\t\t * BAR types are disabled by default.\n+\t\t *\n+\t\t * This is in line with the current EPC core design, where all\n+\t\t * BARs are disabled by default, and then the EPF driver enables\n+\t\t * the BARs it wishes to use.\n+\t\t */\n+\t\tif (bar_type != BAR_RESERVED)\n+\t\t\tdw_pcie_ep_reset_bar(pci, bar);\n+\t}\n+}\n+\n /**\n * dw_pcie_ep_init_registers - Initialize DWC EP specific registers\n * @ep: DWC EP device\n@@ -1187,6 +1209,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)\n \tif (ep->ops->init)\n \t\tep->ops->init(ep);\n \n+\tdw_pcie_ep_disable_bars(ep);\n+\n \t/*\n \t * PCIe r6.0, section 7.9.15 states that for endpoints that support\n \t * PTM, this capability structure is required in exactly one\ndiff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c\nindex 8530746ec5cb..d103ab759c4e 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-plat.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c\n@@ -32,15 +32,6 @@ struct dw_plat_pcie_of_data {\n static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {\n };\n \n-static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)\n-{\n-\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\tenum pci_barno bar;\n-\n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-}\n-\n static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,\n \t\t\t\t unsigned int type, u16 interrupt_num)\n {\n@@ -73,7 +64,6 @@ dw_plat_pcie_get_features(struct dw_pcie_ep *ep)\n }\n \n static const struct dw_pcie_ep_ops pcie_ep_ops = {\n-\t.init = dw_plat_pcie_ep_init,\n \t.raise_irq = dw_plat_pcie_ep_raise_irq,\n \t.get_features = dw_plat_pcie_get_features,\n };\ndiff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c\nindex ecc28093c589..4e9b813c3afb 100644\n--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c\n+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c\n@@ -361,13 +361,9 @@ static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep)\n static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)\n {\n \tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\tenum pci_barno bar;\n \n \trockchip_pcie_enable_l0s(pci);\n \trockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);\n-\n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n };\n \n static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,\ndiff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c\nindex e55675b3840a..e8c8ba1659fd 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c\n@@ -861,17 +861,7 @@ qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)\n \treturn &qcom_pcie_epc_features;\n }\n \n-static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)\n-{\n-\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\tenum pci_barno bar;\n-\n-\tfor (bar = BAR_0; bar <= BAR_5; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-}\n-\n static const struct dw_pcie_ep_ops pci_ep_ops = {\n-\t.init = qcom_pcie_ep_init,\n \t.raise_irq = qcom_pcie_ep_raise_irq,\n \t.get_features = qcom_pcie_epc_get_features,\n };\ndiff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c\nindex 9dd05bac22b9..1198ddc1752c 100644\n--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c\n+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c\n@@ -386,15 +386,6 @@ static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)\n \twritel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);\n }\n \n-static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)\n-{\n-\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\tenum pci_barno bar;\n-\n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-}\n-\n static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar)\n {\n \twritel(0, rcar->base + PCIEDMAINTSTSEN);\n@@ -449,7 +440,6 @@ static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,\n \n static const struct dw_pcie_ep_ops pcie_ep_ops = {\n \t.pre_init = rcar_gen4_pcie_ep_pre_init,\n-\t.init = rcar_gen4_pcie_ep_init,\n \t.raise_irq = rcar_gen4_pcie_ep_raise_irq,\n \t.get_features = rcar_gen4_pcie_ep_get_features,\n \t.get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,\ndiff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/controller/dwc/pcie-stm32-ep.c\nindex c1944b40ce02..a7988dff1045 100644\n--- a/drivers/pci/controller/dwc/pcie-stm32-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c\n@@ -28,15 +28,6 @@ struct stm32_pcie {\n \tunsigned int perst_irq;\n };\n \n-static void stm32_pcie_ep_init(struct dw_pcie_ep *ep)\n-{\n-\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\tenum pci_barno bar;\n-\n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-}\n-\n static int stm32_pcie_start_link(struct dw_pcie *pci)\n {\n \tstruct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);\n@@ -82,7 +73,6 @@ stm32_pcie_get_features(struct dw_pcie_ep *ep)\n }\n \n static const struct dw_pcie_ep_ops stm32_pcie_ep_ops = {\n-\t.init = stm32_pcie_ep_init,\n \t.raise_irq = stm32_pcie_raise_irq,\n \t.get_features = stm32_pcie_get_features,\n };\ndiff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 9f9453e8cd23..3a6bffaff9ea 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1923,15 +1923,6 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)\n \treturn IRQ_HANDLED;\n }\n \n-static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)\n-{\n-\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\tenum pci_barno bar;\n-\n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-};\n-\n static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)\n {\n \t/* Tegra194 supports only INTA */\n@@ -2008,7 +1999,6 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)\n }\n \n static const struct dw_pcie_ep_ops pcie_ep_ops = {\n-\t.init = tegra_pcie_ep_init,\n \t.raise_irq = tegra_pcie_ep_raise_irq,\n \t.get_features = tegra_pcie_ep_get_features,\n };\ndiff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c\nindex 5bde3ee682b5..494376d1812d 100644\n--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c\n@@ -203,15 +203,6 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci)\n \tuniphier_pcie_ltssm_enable(priv, false);\n }\n \n-static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep)\n-{\n-\tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\tenum pci_barno bar;\n-\n-\tfor (bar = BAR_0; bar <= BAR_5; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-}\n-\n static int uniphier_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep)\n {\n \tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n@@ -283,7 +274,6 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep)\n }\n \n static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {\n-\t.init = uniphier_pcie_ep_init,\n \t.raise_irq = uniphier_pcie_ep_raise_irq,\n \t.get_features = uniphier_pcie_get_features,\n };\n", "prefixes": [ "6/9" ] }