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GET /api/patches/2197396/?format=api
{ "id": 2197396, "url": "http://patchwork.ozlabs.org/api/patches/2197396/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260217212707.2450423-12-cassel@kernel.org/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20260217212707.2450423-12-cassel@kernel.org>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20260217212707.2450423-12-cassel@kernel.org/", "date": "2026-02-17T21:27:07", "name": "[1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d6e7acf049e9989d33fa03b431a8ff54260cc5f3", "submitter": { "id": 87751, "url": "http://patchwork.ozlabs.org/api/people/87751/?format=api", "name": "Niklas Cassel", "email": "cassel@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260217212707.2450423-12-cassel@kernel.org/mbox/", "series": [ { "id": 492481, "url": "http://patchwork.ozlabs.org/api/series/492481/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=492481", "date": "2026-02-17T21:27:06", "name": "PCI: endpoint differentiate between disabled and reserved BARs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492481/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197396/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197396/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev+bounces-16920-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=C/fjQHv4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linuxppc-dev+bounces-16920-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n arc=none smtp.remote-ip=172.105.4.254", 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dmarc=pass (p=quarantine dis=none) header.from=kernel.org;\n dkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=C/fjQHv4; dkim-atps=neutral;\n spf=pass (client-ip=172.105.4.254; helo=tor.source.kernel.org;\n envelope-from=cassel@kernel.org;\n receiver=lists.ozlabs.org) smtp.mailfrom=kernel.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1771363666;\n\tbh=X04sYpF9RR3/zBHOQ0h3rIKYAPzRe51nTHAYQKai6UU=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=C/fjQHv4VU1gQU6yfH5Dc/ERiUNHU2+zfHPZhybcyNysepnXxB+HU0uxw+ajqd2to\n\t K3rQE2UoP5GyEf5tiWZ+25juOM5F3fkymp8kmcIHEf5IiTtdh4+ThvOcszMWyVSf+8\n\t Xtc0ZcLcv9CdD2jxQZ4FAgd3m+PxH1IoxpBmS5fAMyOUGSZrFSktZX0Yuf3GEp6ZLG\n\t vLk6zOIWq4TCuarWcuLqT61gfipxN6BoHRCtA+XLTh9qAell6O2aj9qIWBZlgrSAYQ\n\t knyN5RT7FmAPA9kif4tJsGWKcK8v7j1U55zxouA5s/JYML8hGtan/ONQimIkq+Smha\n\t 6QXZvnUsac9vA==", "From": "Niklas Cassel <cassel@kernel.org>", "To": "Minghuan Lian <minghuan.Lian@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>,\n Roy Zang <roy.zang@nxp.com>, Lorenzo Pieralisi <lpieralisi@kernel.org>,\n\t=?utf-8?q?Krzysztof_Wilczy=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Srikanth Thokala <srikanth.thokala@intel.com>,\n Thierry Reding <thierry.reding@gmail.com>,\n Jonathan Hunter <jonathanh@nvidia.com>,\n Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n Masami Hiramatsu <mhiramat@kernel.org>,\n Marek Vasut <marek.vasut+renesas@gmail.com>,\n Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>,\n Geert Uytterhoeven <geert+renesas@glider.be>,\n Magnus Damm <magnus.damm@gmail.com>,\n Kishon Vijay Abraham I <kishon@kernel.org>", "Cc": "Manikanta Maddireddy <mmaddireddy@nvidia.com>,\n\tKoichiro Den <den@valinux.co.jp>,\n\tDamien Le Moal <dlemoal@kernel.org>,\n\tNiklas Cassel <cassel@kernel.org>,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\timx@lists.linux.dev,\n\tlinux-arm-msm@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org,\n\tlinux-renesas-soc@vger.kernel.org", "Subject": "[PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER", "Date": "Tue, 17 Feb 2026 22:27:07 +0100", "Message-ID": "<20260217212707.2450423-12-cassel@kernel.org>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260217212707.2450423-11-cassel@kernel.org>", "References": "<20260217212707.2450423-11-cassel@kernel.org>", "X-Mailing-List": "linuxppc-dev@lists.ozlabs.org", "List-Id": "<linuxppc-dev.lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev+help@lists.ozlabs.org>", "List-Owner": "<mailto:linuxppc-dev+owner@lists.ozlabs.org>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linuxppc-dev/>,\n <https://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Subscribe": "<mailto:linuxppc-dev+subscribe@lists.ozlabs.org>,\n <mailto:linuxppc-dev+subscribe-digest@lists.ozlabs.org>,\n <mailto:linuxppc-dev+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linuxppc-dev+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=7812; i=cassel@kernel.org;\n h=from:subject; bh=X04sYpF9RR3/zBHOQ0h3rIKYAPzRe51nTHAYQKai6UU=;\n b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGDKn3NXRzVUO90+MyMjbePv44dXmDN9EY3oefPviGxPyi\n zeP331BRykLgxgXg6yYIovvD5f9xd3uU44r3rGBmcPKBDKEgYtTACYSsJKR4b9DR/HPG0fmP+mP\n rKou2+w0YcqkbS4vF59+t3r74qIXL5UYGdZr+b29pCFyJ8ta9Z5dgY4d55PNjWs3F8ydwxO8SPz\n ELU4A", "X-Developer-Key": "i=cassel@kernel.org; a=openpgp;\n fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA", "Content-Transfer-Encoding": "8bit", "X-Spam-Status": "No, score=-0.2 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED,\n\tDKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS\n\tautolearn=disabled version=4.0.1 OzLabs 8", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate\nBAR_64BIT_UPPER from BAR_RESERVED.\n\nThis BAR type will only be used for a BAR following a \"only_64bit\" BAR.\n\nThis makes the BAR description more clear, and the reader does no longer\nneed to check the BAR type for the preceding BAR to know how to interpret\nthe BAR type.\n\nNo functional changes.\n\nSigned-off-by: Niklas Cassel <cassel@kernel.org>\n---\n drivers/pci/controller/dwc/pci-layerscape-ep.c | 4 ++--\n drivers/pci/controller/dwc/pcie-keembay.c | 6 +++---\n drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++--\n drivers/pci/controller/dwc/pcie-tegra194.c | 2 +-\n drivers/pci/controller/dwc/pcie-uniphier-ep.c | 10 +++++-----\n drivers/pci/controller/pcie-rcar-ep.c | 6 +++---\n drivers/pci/endpoint/pci-epc-core.c | 3 ++-\n include/linux/pci-epc.h | 5 ++++-\n 8 files changed, 22 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c\nindex a4a800699f89..5a03a8f895f9 100644\n--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c\n+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c\n@@ -251,9 +251,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)\n \tpci->ops = pcie->drvdata->dw_pcie_ops;\n \n \tls_epc->bar[BAR_2].only_64bit = true;\n-\tls_epc->bar[BAR_3].type = BAR_RESERVED;\n+\tls_epc->bar[BAR_3].type = BAR_64BIT_UPPER;\n \tls_epc->bar[BAR_4].only_64bit = true;\n-\tls_epc->bar[BAR_5].type = BAR_RESERVED;\n+\tls_epc->bar[BAR_5].type = BAR_64BIT_UPPER;\n \tls_epc->linkup_notifier = true;\n \n \tpcie->pci = pci;\ndiff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c\nindex 2666a9c3d67e..5a00b8cf5b53 100644\n--- a/drivers/pci/controller/dwc/pcie-keembay.c\n+++ b/drivers/pci/controller/dwc/pcie-keembay.c\n@@ -313,11 +313,11 @@ static const struct pci_epc_features keembay_pcie_epc_features = {\n \t.msi_capable\t\t= true,\n \t.msix_capable\t\t= true,\n \t.bar[BAR_0]\t\t= { .only_64bit = true, },\n-\t.bar[BAR_1]\t\t= { .type = BAR_RESERVED, },\n+\t.bar[BAR_1]\t\t= { .type = BAR_64BIT_UPPER, },\n \t.bar[BAR_2]\t\t= { .only_64bit = true, },\n-\t.bar[BAR_3]\t\t= { .type = BAR_RESERVED, },\n+\t.bar[BAR_3]\t\t= { .type = BAR_64BIT_UPPER, },\n \t.bar[BAR_4]\t\t= { .only_64bit = true, },\n-\t.bar[BAR_5]\t\t= { .type = BAR_RESERVED, },\n+\t.bar[BAR_5]\t\t= { .type = BAR_64BIT_UPPER, },\n \t.align\t\t\t= SZ_16K,\n };\n \ndiff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c\nindex 18460f01b2c6..e55675b3840a 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c\n@@ -850,9 +850,9 @@ static const struct pci_epc_features qcom_pcie_epc_features = {\n \t.msi_capable = true,\n \t.align = SZ_4K,\n \t.bar[BAR_0] = { .only_64bit = true, },\n-\t.bar[BAR_1] = { .type = BAR_RESERVED, },\n+\t.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },\n \t.bar[BAR_2] = { .only_64bit = true, },\n-\t.bar[BAR_3] = { .type = BAR_RESERVED, },\n+\t.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },\n };\n \n static const struct pci_epc_features *\ndiff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 06571d806ab3..31aa9a494dbc 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1993,7 +1993,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {\n \t.msi_capable = true,\n \t.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,\n \t\t\t.only_64bit = true, },\n-\t.bar[BAR_1] = { .type = BAR_RESERVED, },\n+\t.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },\n \t.bar[BAR_2] = { .type = BAR_RESERVED, },\n \t.bar[BAR_3] = { .type = BAR_RESERVED, },\n \t.bar[BAR_4] = { .type = BAR_RESERVED, },\ndiff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c\nindex d52753060970..f873a1659592 100644\n--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c\n+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c\n@@ -426,9 +426,9 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {\n \t\t.msix_capable = false,\n \t\t.align = 1 << 16,\n \t\t.bar[BAR_0] = { .only_64bit = true, },\n-\t\t.bar[BAR_1] = { .type = BAR_RESERVED, },\n+\t\t.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },\n \t\t.bar[BAR_2] = { .only_64bit = true, },\n-\t\t.bar[BAR_3] = { .type = BAR_RESERVED, },\n+\t\t.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },\n \t\t.bar[BAR_4] = { .type = BAR_RESERVED, },\n \t\t.bar[BAR_5] = { .type = BAR_RESERVED, },\n \t},\n@@ -445,11 +445,11 @@ static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {\n \t\t.msix_capable = false,\n \t\t.align = 1 << 12,\n \t\t.bar[BAR_0] = { .only_64bit = true, },\n-\t\t.bar[BAR_1] = { .type = BAR_RESERVED, },\n+\t\t.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },\n \t\t.bar[BAR_2] = { .only_64bit = true, },\n-\t\t.bar[BAR_3] = { .type = BAR_RESERVED, },\n+\t\t.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },\n \t\t.bar[BAR_4] = { .only_64bit = true, },\n-\t\t.bar[BAR_5] = { .type = BAR_RESERVED, },\n+\t\t.bar[BAR_5] = { .type = BAR_64BIT_UPPER, },\n \t},\n };\n \ndiff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c\nindex 657875ef4657..9b3f5391fabe 100644\n--- a/drivers/pci/controller/pcie-rcar-ep.c\n+++ b/drivers/pci/controller/pcie-rcar-ep.c\n@@ -440,13 +440,13 @@ static const struct pci_epc_features rcar_pcie_epc_features = {\n \t/* use 64-bit BARs so mark BAR[1,3,5] as reserved */\n \t.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = 128,\n \t\t\t.only_64bit = true, },\n-\t.bar[BAR_1] = { .type = BAR_RESERVED, },\n+\t.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },\n \t.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = 256,\n \t\t\t.only_64bit = true, },\n-\t.bar[BAR_3] = { .type = BAR_RESERVED, },\n+\t.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },\n \t.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256,\n \t\t\t.only_64bit = true, },\n-\t.bar[BAR_5] = { .type = BAR_RESERVED, },\n+\t.bar[BAR_5] = { .type = BAR_64BIT_UPPER, },\n };\n \n static const struct pci_epc_features*\ndiff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c\nindex 068155819c57..8de321e1c342 100644\n--- a/drivers/pci/endpoint/pci-epc-core.c\n+++ b/drivers/pci/endpoint/pci-epc-core.c\n@@ -104,7 +104,8 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features\n \n \tfor (i = bar; i < PCI_STD_NUM_BARS; i++) {\n \t\t/* If the BAR is not reserved, return it. */\n-\t\tif (epc_features->bar[i].type != BAR_RESERVED)\n+\t\tif (epc_features->bar[i].type != BAR_RESERVED &&\n+\t\t epc_features->bar[i].type != BAR_64BIT_UPPER)\n \t\t\treturn i;\n \t}\n \ndiff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h\nindex c021c7af175f..c22f8a6cf9a3 100644\n--- a/include/linux/pci-epc.h\n+++ b/include/linux/pci-epc.h\n@@ -192,12 +192,15 @@ struct pci_epc {\n *\t\t NOTE: An EPC driver can currently only set a single supported\n *\t\t size.\n * @BAR_RESERVED: The BAR should not be touched by an EPF driver.\n+ * @BAR_64BIT_UPPER: Should only be set on a BAR if the preceding BAR is marked\n+ *\t\t as only_64bit.\n */\n enum pci_epc_bar_type {\n \tBAR_PROGRAMMABLE = 0,\n \tBAR_FIXED,\n \tBAR_RESIZABLE,\n \tBAR_RESERVED,\n+\tBAR_64BIT_UPPER,\n };\n \n /**\n@@ -207,7 +210,7 @@ enum pci_epc_bar_type {\n * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR\n *\t\tshould be configured as 32-bit or 64-bit, the EPF driver must\n *\t\tconfigure this BAR as 64-bit. Additionally, the BAR succeeding\n- *\t\tthis BAR must be set to type BAR_RESERVED.\n+ *\t\tthis BAR must be set to type BAR_64BIT_UPPER.\n *\n *\t\tonly_64bit should not be set on a BAR of type BAR_RESERVED.\n *\t\t(If BARx is a 64-bit BAR that an EPF driver is not allowed to\n", "prefixes": [ "1/9" ] }