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GET /api/patches/2197252/?format=api
{ "id": 2197252, "url": "http://patchwork.ozlabs.org/api/patches/2197252/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260217153010.408739-2-ankita@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217153010.408739-2-ankita@nvidia.com>", "list_archive_url": null, "date": "2026-02-17T15:30:08", "name": "[v4,1/3] hw/vfio: sort and validate sparse mmap regions by offset", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5d83a7fd8c315c33bd934c90bee52d7fabfa2393", "submitter": { "id": 86155, "url": "http://patchwork.ozlabs.org/api/people/86155/?format=api", "name": "Ankit Agrawal", "email": "ankita@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260217153010.408739-2-ankita@nvidia.com/mbox/", "series": [ { "id": 492441, "url": "http://patchwork.ozlabs.org/api/series/492441/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492441", "date": "2026-02-17T15:30:09", "name": "hw/vfio: Enable hugepfnmap for non-power-of-2 device memory regions", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/492441/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197252/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197252/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=S0WC6Q8o;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c105::1;\n envelope-from=ankita@nvidia.com;\n helo=CH1PR05CU001.outbound.protection.outlook.com" ], "From": "<ankita@nvidia.com>", "To": "<ankita@nvidia.com>, <vsethi@nvidia.com>, <jgg@nvidia.com>,\n <skolothumtho@nvidia.com>, <alex@shazbot.org>, <clg@redhat.com>", "CC": "<aniketa@nvidia.com>, <cjia@nvidia.com>, <kwankhede@nvidia.com>,\n <targupta@nvidia.com>, <zhiw@nvidia.com>, <mochs@nvidia.com>,\n <kjaju@nvidia.com>, <qemu-devel@nongnu.org>", "Subject": "[PATCH v4 1/3] hw/vfio: sort and validate sparse mmap regions by\n offset", "Date": "Tue, 17 Feb 2026 15:30:08 +0000", "Message-ID": "<20260217153010.408739-2-ankita@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260217153010.408739-1-ankita@nvidia.com>", "References": "<20260217153010.408739-1-ankita@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN3PEPF0000B373:EE_|CH8PR12MB9837:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b52db2f2-3377-4afc-6061-08de6e398267", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|1800799024|82310400026|36860700013|7053199007;", "X-Microsoft-Antispam-Message-Info": "\n 3NDSMjlxu4pfdnrSKSmDREuk4w+sSLP6e2A8xjRGi05iDb2Zr9u2RI4826fIZbT3Kzb/xyf+M7Nm7yBKailh801AGiM7Etwp8qeMm5tnl7MhzoPjNp1R0hUAauXCEjXDTg2zGQ0EZ6CnJPSNlJptW7Ma8Z3ZjcGrMa1z/GlNgtWnyBB3Ul2ZZ54EDhWcRBb+QP9Z8GeNavNIv/6G5Mx6Y73N7OQ6rnBzmFNR77X0sCEWj9661Rq2ttD5m4ECH665FKcTRzhcW+kRM7R0uXUuCXyeQAgTQRuyrqi9XK3ei9gt68AatwUQo6hhmszI7NqoY3b8RHtJly6k3Xq4UsMreaOlW4W/zPJSmbYKWBpCq60e2LSSqt28LjOaz0TbtJ/t61UHGb5bCsNHvgHfnubTYtSrB4/owT/FFCEiYfLHppks2DM9ie2dQQ3VAYccgKu5xf6KgE6KSZnEjGJcJzb2CtxyWoi7TOQHQ1z7wJfXIorsaR37aiEmODzNHhuzvvgLzuXKMYirWJ7DZ+iNqtcrNz64oLcmub4JDN+oe+2WlSwsRl+Feoy6RksoYv/OuodMufYFiOY0a2DRmQBQD9o6f1iUz7g4AQOIsqHX4hThf07Xwm1Do7VzcwZkjgTZBe8MQbHvrbJopFueLlE3Cj7KDXh5dXED5xEOpovybQsGb6nlcUuXm8dyLdGt5LLzMelHCS/Aoo04UKTdeOScJ4WrHEwETa/z7ZGhNSYhN27H/IDMtjSBXL7M3KeMkXxTS904N+HfJVO8soWl2TRTT4E4Y3HorRuhrV5v6QTVMe9DeoumlcNf0716YemmXrzIVsBjHCCULj4rYqUZI/G/avzee4ERrsoA77b7IvjzTe/YKAsGsqqAF6M6qVxPOY3CkgUbifP0ZKpOE492Mw0RmBFBaPXWAuXkx32w9qD8EtOKq5Mv9FfQMcA65TM5yooGcCKr4iQ+Fcm2u/YPqltKNwg/omnEen8OlYi1qb+DJgPJTPCpPYOS/bTYgQ9JaF3PsyXBXNXn8LNaq9ElS5Z4TI5+c2e5f0OLI11/hg3b/7jienHowSjC4j9OzDbYNIVKageQfymrJL0DX5Y+gCnq9ASpkIruqZCnNK+sO/O7OdBOcWmPewhg1RZk7oYMzN6imszkkWvuUMbbfXeiHvRXkILifFFnRY78fZydBoTaL9aVmjX1qgkP6pZFiHumNP7694Q0aLAaSABTslslGXcS+zmlXOWFfzmGHnbwcnykakTep4kRRXgIHPmKjHY5Jchoh6v+aRkLgsUz8ooeNA9K3BbLaJnG2bEde/Xc88X379RtfepDpPRgO+jGyllJlgFFYIdKRJ34kok5yu1SU9s3pCd3JorYlMqyGOUlB7+u932sVGlpZre7nnay13TJ/dLRT5nOiv1XTgSRflsIO5OjqX+u04RCRUkVkiiJ/6LsV8mA6Q0H6DRidRsgIgtcHyVJp94VRnppTM9BmC1pCnU5N6ZUQ8EIQ55fFoEJUTPEvkI8zcL0ECHwhy/cHXMNBWtTtxu3dQ4hHF0T1iJ5psrbzTmRr/yN5pe50sxxZu8Rm2RRVqklZkDvEeHSx+f0UX46pCt3c+gZH8e5aTD8kp2zXDJ/SVgew3sn1c2vWS+TNJHhPp1nHAmjDombS1qHZvVen8YKpypMilathSmz2b4Dkuw50Q==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN3PEPF0000B373.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH8PR12MB9837", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Ankit Agrawal <ankita@nvidia.com>\n\nSort sparse mmap regions by offset during region setup to ensure\npredictable mapping order, avoid overlaps and a proper handling\nof the gaps between sub-regions.\n\nAdd validation to detect overlapping sparse regions early during\nsetup before any mapping operations begin.\n\nThe sorting is performed on the subregions ranges during\nvfio_setup_region_sparse_mmaps(). This also ensures that subsequent\nmapping code can rely on subregions being in ascending offset order.\n\nThis is preparatory work for alignment adjustments needed to support\nhugepfnmap on systems where device memory (e.g., Grace-based systems)\nmay have non-power-of-2 sizes.\n\ncc: Alex Williamson <alex@shazbot.org>\nReviewed-by: Alex Williamson <alex@shazbot.org>\nReviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Ankit Agrawal <ankita@nvidia.com>\n---\n hw/vfio/region.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-\n 1 file changed, 45 insertions(+), 1 deletion(-)", "diff": "diff --git a/hw/vfio/region.c b/hw/vfio/region.c\nindex ab39d77574..8fbc98918f 100644\n--- a/hw/vfio/region.c\n+++ b/hw/vfio/region.c\n@@ -149,6 +149,19 @@ static const MemoryRegionOps vfio_region_ops = {\n },\n };\n \n+static int vfio_mmap_compare_offset(const void *a, const void *b)\n+{\n+ const VFIOMmap *mmap_a = a;\n+ const VFIOMmap *mmap_b = b;\n+\n+ if (mmap_a->offset < mmap_b->offset) {\n+ return -1;\n+ } else if (mmap_a->offset > mmap_b->offset) {\n+ return 1;\n+ }\n+ return 0;\n+}\n+\n static int vfio_setup_region_sparse_mmaps(VFIORegion *region,\n struct vfio_region_info *info)\n {\n@@ -182,6 +195,35 @@ static int vfio_setup_region_sparse_mmaps(VFIORegion *region,\n region->nr_mmaps = j;\n region->mmaps = g_realloc(region->mmaps, j * sizeof(VFIOMmap));\n \n+ /*\n+ * Sort sparse mmaps by offset to ensure proper handling of gaps\n+ * and predictable mapping order in vfio_region_mmap().\n+ */\n+ if (region->nr_mmaps > 1) {\n+ qsort(region->mmaps, region->nr_mmaps, sizeof(VFIOMmap),\n+ vfio_mmap_compare_offset);\n+\n+ /*\n+ * Validate that sparse regions don't overlap after sorting.\n+ */\n+ for (i = 1; i < region->nr_mmaps; i++) {\n+ off_t prev_end = region->mmaps[i - 1].offset +\n+ region->mmaps[i - 1].size;\n+ if (prev_end > region->mmaps[i].offset) {\n+ error_report(\"%s: overlapping sparse mmap regions detected \"\n+ \"in region %d: [0x%\"PRIx64\"-0x%\"PRIx64\"] overlaps \"\n+ \"with [0x%\"PRIx64\"-0x%\"PRIx64\"]\",\n+ __func__, region->nr, region->mmaps[i - 1].offset,\n+ prev_end - 1, region->mmaps[i].offset,\n+ region->mmaps[i].offset + region->mmaps[i].size - 1);\n+ g_free(region->mmaps);\n+ region->mmaps = NULL;\n+ region->nr_mmaps = 0;\n+ return -EINVAL;\n+ }\n+ }\n+ }\n+\n return 0;\n }\n \n@@ -213,11 +255,13 @@ int vfio_region_setup(Object *obj, VFIODevice *vbasedev, VFIORegion *region,\n \n ret = vfio_setup_region_sparse_mmaps(region, info);\n \n- if (ret) {\n+ if (ret == -ENODEV) {\n region->nr_mmaps = 1;\n region->mmaps = g_new0(VFIOMmap, region->nr_mmaps);\n region->mmaps[0].offset = 0;\n region->mmaps[0].size = region->size;\n+ } else if (ret) {\n+ return ret;\n }\n }\n }\n", "prefixes": [ "v4", "1/3" ] }