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GET /api/patches/2197164/?format=api
{ "id": 2197164, "url": "http://patchwork.ozlabs.org/api/patches/2197164/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260217-soc-tegra-arch-kconfig-v1-1-81bf5674d032@oss.qualcomm.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217-soc-tegra-arch-kconfig-v1-1-81bf5674d032@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-02-17T09:16:36", "name": "[1/3] soc: tegra: Make ARCH_TEGRA_SOC_FOO defaults for Nvidia Tegra", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "52cf0d1b5cac5fbc7c3117fca2d915385b659f74", "submitter": { "id": 92171, "url": "http://patchwork.ozlabs.org/api/people/92171/?format=api", "name": "Krzysztof Kozlowski", "email": "krzysztof.kozlowski@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260217-soc-tegra-arch-kconfig-v1-1-81bf5674d032@oss.qualcomm.com/mbox/", "series": [ { "id": 492400, "url": "http://patchwork.ozlabs.org/api/series/492400/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=492400", "date": "2026-02-17T09:16:35", "name": "arm64: tegra: Make ARCH_TEGRA_SOC_FOO defaults for Nvidia Tegra", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492400/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197164/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197164/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11987-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=jJ8Yn9Un;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Yd+dGkqq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260217-soc-tegra-arch-kconfig-v1-1-81bf5674d032@oss.qualcomm.com>", "References": "\n <20260217-soc-tegra-arch-kconfig-v1-0-81bf5674d032@oss.qualcomm.com>", "In-Reply-To": "\n <20260217-soc-tegra-arch-kconfig-v1-0-81bf5674d032@oss.qualcomm.com>", "To": "Thierry Reding <thierry.reding@kernel.org>,\n Jonathan Hunter <jonathanh@nvidia.com>,\n Russell King <linux@armlinux.org.uk>", "Cc": "linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-kernel@lists.infradead.org, Arnd Bergmann <arnd@arndb.de>,\n Alexandre Belloni <alexandre.belloni@bootlin.com>,\n Linus Walleij <linusw@kernel.org>, Drew Fustini <fustini@kernel.org>,\n Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=3335;\n i=krzysztof.kozlowski@oss.qualcomm.com; h=from:subject:message-id;\n bh=bqDjRxVs8N/Q5ZrspI/TWkpKsVqj7iN896A7uBcshw0=;\n b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBplDH6QW+MOGCK5XyT7x1kVp4DNOhOLdnK6TVMv\n BpFEjy80U2JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaZQx+gAKCRDBN2bmhouD\n 13xYD/wKO+BcroimNHNVHXfTzxMAdsHpdxdSyXcF9pUbPY2oQzXZhCeNZQ95N3PGXXGtGEdA2sU\n VYNwe8bfPQq2H6BWRF3kdjktdRb0+3F2lOXks0lp+OIa110eR1fLVlWbboeEA1g5lGT5ZH/eXw/\n HtxIii4cJOLOlxcbExjmELSHPi/TqG+l0fRTAzhkijw81BiEFaIymfzwkeyoIN9OAgt7tR6abIU\n +2HeIZ/J6jC6ag5oHdbPGNfpd7g3dibnsny+R6+vFzSbtIePyC4MYY3jXlTwfLsHfHS9oQLrmYV\n uGjKmcjCfHXp/zAswYvGiw/zItZcX+e8DJ2v+RO74admlyQFrU6Ep0bx/oKUoJ0ap05uqrzISH/\n 5cL5GngRhrxlL0mmcI16cYOqQfiF7bw0E7WSRecxGpgDFLhi7Q3Nmk4N6fbqExU4+hteG8pty/+\n W9tlaKq40/dF2pw1hvjpKcurIu7Ft2fzRytGuTl3F3nyJbZxuvpMk09SeiqdgGeXXt4axqCjGvV\n saO0/OILpRir1Vi5ja69lepqKYmORg4xsizXP/hTBjOSgEDPnOLnICLGFevcoFruMOiIzJfP1Nc\n qsraCPxElbRgzPyyLNRPrqUreVV9k5VAoveMFXcfA2Y2e16mj7qSwqcNlLnoWp3DqtI9eyuibn1\n I4srIXHmRPhuPuA==", "X-Developer-Key": "i=krzysztof.kozlowski@oss.qualcomm.com; a=openpgp;\n fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B", "X-Proofpoint-GUID": "VrYnTRAMMks-KRI7B9rBuS6hrjCqnrPK", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMjE3MDA3NiBTYWx0ZWRfX3o3VAJJvWHou\n CAvI+hlt02kU1CUMGQ8skDYpVETuXtNSIl2QmDczilg/Wn8iXx2Xo5y3v8zJElD/oEL107e6GWh\n i8F/ts9BQGh7BXBTzyb2u8SdXi9AYq2nTjd4BYd6ufDR+5ghf+6QjfOepmWAvqBDimqmcpbB9d0\n q7pxfrKmsV+AqzNNNk6XACxRJglyY8TomFQAryNWWayC/xjJ+7CZDINDs/gXq7yt6tRR2IoxCR8\n tey/ke5IkTbrB2qhZWUk76t4exKJmDYJa+mPlWrcI8yasuL3NLE6tRbl7ja+mfR2oq1q3zH2dLP\n 67eGI0wsdyIbSQGK7/t9pa6sk4QwdfUi5fAp9t65stOjx9jBm/4isjtQ8IYd+SURhhzjUqr6kOC\n 6w7rVrissEfTuI3vWj7AS4fvD6/1Ov3Ch8ph2NEUx3CU2SnwG48Vxx/Ecc4YRLCc49HzfQao7OI\n rXSgerV2WIN6th4d4CQ==", "X-Authority-Analysis": "v=2.4 cv=BpuQAIX5 c=1 sm=1 tr=0 ts=69943201 cx=c_pps\n a=qKBjSQ1v91RyAK45QCPf5w==:117 a=6nO30s3o7FuWeffXwhKHTA==:17\n a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22\n a=EUspDBNiAAAA:8 a=H7KHO4RPsEdM4UCB5m0A:9 a=isR4AqL0EaFW8Alr:21\n a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22", "X-Proofpoint-ORIG-GUID": "VrYnTRAMMks-KRI7B9rBuS6hrjCqnrPK", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-02-17_01,2026-02-16_04,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 priorityscore=1501 adultscore=0 clxscore=1015 phishscore=0\n lowpriorityscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602170076" }, "content": "By convention, only one globally selectable ARCH_PLATFORM is expected\nfor given SoC platform, defined in arch/arm64/Kconfig.platforms or\narch/arm/mach-*/Kconfig, because we target a single multi-platform\nkernel image.\n\nPlatforms wanting different granularity, e.g. due to size constraints on\ntheir devices, should be sure that globally only one ARCH_PLTAFORM is\nselected in defconfig. Change Tegra per-soc Kconfig entries to default\nto ARCH_TEGRA allowing removal of these per-soc parts from defconfigs.\n\nSigned-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>\n\n---\n\n1. All further patches depend on this one.\n2. Year ago after my complains Prabhakar fixed another case - Renesas -\n so with this patch we get rid of all single-ARCH offenders.\n---\n drivers/soc/tegra/Kconfig | 11 +++++++++++\n 1 file changed, 11 insertions(+)", "diff": "diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig\nindex c0fc54c3cd35..a1cadfdb356c 100644\n--- a/drivers/soc/tegra/Kconfig\n+++ b/drivers/soc/tegra/Kconfig\n@@ -6,6 +6,7 @@ if ARM\n \n config ARCH_TEGRA_2x_SOC\n \tbool \"Enable support for Tegra20 family\"\n+\tdefault ARCH_TEGRA\n \tselect ARCH_NEEDS_CPU_IDLE_COUPLED if SMP\n \tselect ARM_ERRATA_720789\n \tselect ARM_ERRATA_754327 if SMP\n@@ -23,6 +24,7 @@ config ARCH_TEGRA_2x_SOC\n \n config ARCH_TEGRA_3x_SOC\n \tbool \"Enable support for Tegra30 family\"\n+\tdefault ARCH_TEGRA\n \tselect ARM_ERRATA_754322\n \tselect ARM_ERRATA_764369 if SMP\n \tselect PINCTRL_TEGRA30\n@@ -37,6 +39,7 @@ config ARCH_TEGRA_3x_SOC\n \n config ARCH_TEGRA_114_SOC\n \tbool \"Enable support for Tegra114 family\"\n+\tdefault ARCH_TEGRA\n \tselect ARM_ERRATA_798181 if SMP\n \tselect HAVE_ARM_ARCH_TIMER\n \tselect PINCTRL_TEGRA114\n@@ -49,6 +52,7 @@ config ARCH_TEGRA_114_SOC\n \n config ARCH_TEGRA_124_SOC\n \tbool \"Enable support for Tegra124 family\"\n+\tdefault ARCH_TEGRA\n \tselect HAVE_ARM_ARCH_TIMER\n \tselect PINCTRL_TEGRA124\n \tselect SOC_TEGRA_FLOWCTRL\n@@ -65,6 +69,7 @@ if ARM64\n \n config ARCH_TEGRA_132_SOC\n \tbool \"NVIDIA Tegra132 SoC\"\n+\tdefault ARCH_TEGRA\n \tselect PINCTRL_TEGRA124\n \tselect SOC_TEGRA_FLOWCTRL\n \tselect SOC_TEGRA_PMC\n@@ -76,6 +81,7 @@ config ARCH_TEGRA_132_SOC\n \n config ARCH_TEGRA_210_SOC\n \tbool \"NVIDIA Tegra210 SoC\"\n+\tdefault ARCH_TEGRA\n \tselect PINCTRL_TEGRA210\n \tselect SOC_TEGRA_FLOWCTRL\n \tselect SOC_TEGRA_PMC\n@@ -95,6 +101,7 @@ config ARCH_TEGRA_210_SOC\n \n config ARCH_TEGRA_186_SOC\n \tbool \"NVIDIA Tegra186 SoC\"\n+\tdefault ARCH_TEGRA\n \tdepends on !CPU_BIG_ENDIAN\n \tselect PINCTRL_TEGRA186\n \tselect MAILBOX\n@@ -109,6 +116,7 @@ config ARCH_TEGRA_186_SOC\n \n config ARCH_TEGRA_194_SOC\n \tbool \"NVIDIA Tegra194 SoC\"\n+\tdefault ARCH_TEGRA\n \tdepends on !CPU_BIG_ENDIAN\n \tselect MAILBOX\n \tselect PINCTRL_TEGRA194\n@@ -118,6 +126,7 @@ config ARCH_TEGRA_194_SOC\n \n config ARCH_TEGRA_234_SOC\n \tbool \"NVIDIA Tegra234 SoC\"\n+\tdefault ARCH_TEGRA\n \tdepends on !CPU_BIG_ENDIAN\n \tselect MAILBOX\n \tselect PINCTRL_TEGRA234\n@@ -127,11 +136,13 @@ config ARCH_TEGRA_234_SOC\n \n config ARCH_TEGRA_241_SOC\n \tbool \"NVIDIA Tegra241 SoC\"\n+\tdefault ARCH_TEGRA\n \thelp\n \t Enable support for the NVIDIA Tegra241 SoC.\n \n config ARCH_TEGRA_264_SOC\n \tbool \"NVIDIA Tegra264 SoC\"\n+\tdefault ARCH_TEGRA\n \tdepends on !CPU_BIG_ENDIAN\n \tselect MAILBOX\n \tselect SOC_TEGRA_PMC\n", "prefixes": [ "1/3" ] }