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{
    "id": 2197143,
    "url": "http://patchwork.ozlabs.org/api/patches/2197143/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217080601.3808847-5-den@valinux.co.jp/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
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    "msgid": "<20260217080601.3808847-5-den@valinux.co.jp>",
    "list_archive_url": null,
    "date": "2026-02-17T08:05:56",
    "name": "[v8,4/9] PCI: dwc: Record integrated eDMA register window",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "981bb241d0180d4809748f98c919e4076d16bb26",
    "submitter": {
        "id": 91573,
        "url": "http://patchwork.ozlabs.org/api/people/91573/?format=api",
        "name": "Koichiro Den",
        "email": "den@valinux.co.jp"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217080601.3808847-5-den@valinux.co.jp/mbox/",
    "series": [
        {
            "id": 492390,
            "url": "http://patchwork.ozlabs.org/api/series/492390/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492390",
            "date": "2026-02-17T08:05:52",
            "name": "PCI: endpoint: pci-ep-msi: Add embedded doorbell fallback",
            "version": 8,
            "mbox": "http://patchwork.ozlabs.org/series/492390/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2197143/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2197143/checks/",
    "tags": {},
    "related": [],
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        "From": "Koichiro Den <den@valinux.co.jp>",
        "To": "jingoohan1@gmail.com,\n\tmani@kernel.org,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\trobh@kernel.org,\n\tbhelgaas@google.com,\n\theiko@sntech.de,\n\tkishon@kernel.org,\n\tjdmason@kudzu.us,\n\tdave.jiang@intel.com,\n\tallenbh@gmail.com,\n\tcassel@kernel.org,\n\tshawn.lin@rock-chips.com,\n\tFrank.Li@nxp.com",
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        "Subject": "[PATCH v8 4/9] PCI: dwc: Record integrated eDMA register window",
        "Date": "Tue, 17 Feb 2026 17:05:56 +0900",
        "Message-ID": "<20260217080601.3808847-5-den@valinux.co.jp>",
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    },
    "content": "Some DesignWare PCIe controllers integrate an eDMA block whose registers\nare located in a dedicated register window. Endpoint function drivers\nmay need the physical base and size of this window to map/expose it to a\npeer.\n\nRecord the physical base and size of the integrated eDMA register window\nin struct dw_pcie.\n\nReviewed-by: Frank Li <Frank.Li@nxp.com>\nSigned-off-by: Koichiro Den <den@valinux.co.jp>\n---\n drivers/pci/controller/dwc/pcie-designware.c | 4 ++++\n drivers/pci/controller/dwc/pcie-designware.h | 2 ++\n 2 files changed, 6 insertions(+)",
    "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex 5741c09dde7f..f82ed189f6ae 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -162,8 +162,12 @@ int dw_pcie_get_resources(struct dw_pcie *pci)\n \t\t\tpci->edma.reg_base = devm_ioremap_resource(pci->dev, res);\n \t\t\tif (IS_ERR(pci->edma.reg_base))\n \t\t\t\treturn PTR_ERR(pci->edma.reg_base);\n+\t\t\tpci->edma_reg_phys = res->start;\n+\t\t\tpci->edma_reg_size = resource_size(res);\n \t\t} else if (pci->atu_size >= 2 * DEFAULT_DBI_DMA_OFFSET) {\n \t\t\tpci->edma.reg_base = pci->atu_base + DEFAULT_DBI_DMA_OFFSET;\n+\t\t\tpci->edma_reg_phys = pci->atu_phys_addr + DEFAULT_DBI_DMA_OFFSET;\n+\t\t\tpci->edma_reg_size = pci->atu_size - DEFAULT_DBI_DMA_OFFSET;\n \t\t}\n \t}\n \ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex ae6389dd9caa..52f26663e8b1 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -541,6 +541,8 @@ struct dw_pcie {\n \tint\t\t\tmax_link_speed;\n \tu8\t\t\tn_fts[2];\n \tstruct dw_edma_chip\tedma;\n+\tphys_addr_t\t\tedma_reg_phys;\n+\tresource_size_t\t\tedma_reg_size;\n \tbool\t\t\tl1ss_support;\t/* L1 PM Substates support */\n \tstruct clk_bulk_data\tapp_clks[DW_PCIE_NUM_APP_CLKS];\n \tstruct clk_bulk_data\tcore_clks[DW_PCIE_NUM_CORE_CLKS];\n",
    "prefixes": [
        "v8",
        "4/9"
    ]
}