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GET /api/patches/2197137/?format=api
{ "id": 2197137, "url": "http://patchwork.ozlabs.org/api/patches/2197137/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217080102.206581-6-sunlightlinux@gmail.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217080102.206581-6-sunlightlinux@gmail.com>", "list_archive_url": null, "date": "2026-02-17T08:01:00", "name": "[RFC,2/3] PCI: Add PCIe Gen 7 (128 GT/s) speed detection and reporting", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "64b3954bd0ec6d3bd07944bd51cfe5f6000860a7", "submitter": { "id": 92653, "url": "http://patchwork.ozlabs.org/api/people/92653/?format=api", "name": "Ionut Nechita (Sunlight Linux)", "email": "sunlightlinux@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217080102.206581-6-sunlightlinux@gmail.com/mbox/", "series": [ { "id": 492389, "url": "http://patchwork.ozlabs.org/api/series/492389/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492389", "date": "2026-02-17T08:00:56", "name": "PCI: Add PCIe Gen 7 (128 GT/s) speed support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492389/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197137/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197137/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47423-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=YQtYpjli;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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Wysocki\" <rafael@kernel.org>,\n Daniel Lezcano <daniel.lezcano@linaro.org>", "Cc": "Zhang Rui <rui.zhang@intel.com>,\n\tLukasz Luba <lukasz.luba@arm.com>,\n\tLukas Wunner <lukas@wunner.de>,\n\tIonut Nechita <sunlightlinux@gmail.com>,\n\tlinux-pci@vger.kernel.org,\n\tlinux-pm@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tIonut Nechita <ionut_n2001@yahoo.com>", "Subject": "[RFC PATCH 2/3] PCI: Add PCIe Gen 7 (128 GT/s) speed detection and\n reporting", "Date": "Tue, 17 Feb 2026 10:01:00 +0200", "Message-ID": "<20260217080102.206581-6-sunlightlinux@gmail.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260217080102.206581-2-sunlightlinux@gmail.com>", "References": "<20260217080102.206581-2-sunlightlinux@gmail.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Ionut Nechita <ionut_n2001@yahoo.com>\n\nAdd kernel infrastructure to detect and report PCIe Gen 7 128 GT/s\nlink speeds:\n\n - Extend PCIE_LNKCAP_SLS2SPEED, PCIE_LNKCAP2_SLS2SPEED, and\n PCIE_LNKCTL2_TLS2SPEED macros with 128 GT/s mapping\n - Add 128 GT/s to PCIE_SPEED2MBS_ENC bandwidth calculation using\n 1:1 Flit mode encoding (no overhead), consistent with Gen 6\n - Add PCIE_SPEED_128_0GT to pcie_dev_speed_mbps() switch\n - Map link speed encoding 7 to PCIE_SPEED_128_0GT in\n pcie_link_speed[] table\n - Add \"128.0 GT/s PCIe\" display string\n - Add pcie_speed_requires_flit() helper for Gen 6+ speed\n validation with proper range check against PCI_SPEED_UNKNOWN\n - Widen pcie_get_supported_speeds() return type from u8 to u16\n - Add Flit mode diagnostic warning when Gen 6+ speed is active\n but PCI_EXP_LNKSTA2_FLIT is not set\n\nSigned-off-by: Ionut Nechita <ionut_n2001@yahoo.com>\n---\n drivers/pci/pci.c | 7 +++++--\n drivers/pci/pci.h | 28 ++++++++++++++++++++++------\n drivers/pci/probe.c | 3 ++-\n 3 files changed, 29 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex 13dbb405dc31f..8091f7bf30e6f 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -5912,10 +5912,10 @@ EXPORT_SYMBOL(pcie_bandwidth_available);\n *\n * Return: Supported Link Speeds Vector (+ reserved 0 at LSB).\n */\n-u8 pcie_get_supported_speeds(struct pci_dev *dev)\n+u16 pcie_get_supported_speeds(struct pci_dev *dev)\n {\n \tu32 lnkcap2, lnkcap;\n-\tu8 speeds;\n+\tu16 speeds;\n \n \t/*\n \t * Speeds retain the reserved 0 at LSB before PCIe Supported Link\n@@ -6020,6 +6020,9 @@ void __pcie_print_link_status(struct pci_dev *dev, bool verbose)\n \n \tif (dev->bus && dev->bus->flit_mode)\n \t\tflit_mode = \", in Flit mode\";\n+\telse if (dev->bus && pcie_speed_requires_flit(dev->bus->cur_bus_speed))\n+\t\tpci_warn(dev, \"Flit mode not active at %s, expected for Gen 6+\\n\",\n+\t\t\t pci_speed_string(dev->bus->cur_bus_speed));\n \n \tif (bw_avail >= bw_cap && verbose)\n \t\tpci_info(dev, \"%u.%03u Gb/s available PCIe bandwidth (%s x%d link)%s\\n\",\ndiff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex 60542b05de0c6..4dd23f0d5de9f 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -487,7 +487,8 @@ void pci_bus_put(struct pci_bus *bus);\n ({\t\t\t\t\t\t\t\t\t\\\n \tu32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS;\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\t(lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT :\t\\\n+\t(lnkcap_sls == PCI_EXP_LNKCAP_SLS_128_0GB ? PCIE_SPEED_128_0GT :\t\\\n+\t lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT :\t\\\n \t lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT :\t\\\n \t lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT :\t\\\n \t lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT :\t\\\n@@ -498,7 +499,8 @@ void pci_bus_put(struct pci_bus *bus);\n \n /* PCIe link information from Link Capabilities 2 */\n #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \\\n-\t((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \\\n+\t((lnkcap2) & PCI_EXP_LNKCAP2_SLS_128_0GB ? PCIE_SPEED_128_0GT : \\\n+\t (lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \\\n \t (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \\\n \t (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \\\n \t (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \\\n@@ -510,7 +512,8 @@ void pci_bus_put(struct pci_bus *bus);\n ({\t\t\t\t\t\t\t\t\t\\\n \tu16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS;\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n-\t(lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT :\t\\\n+\t(lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_128_0GT ? PCIE_SPEED_128_0GT :\t\\\n+\t lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT :\t\\\n \t lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT :\t\\\n \t lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT :\t\\\n \t lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT :\t\\\n@@ -519,9 +522,14 @@ void pci_bus_put(struct pci_bus *bus);\n \t PCI_SPEED_UNKNOWN);\t\t\t\t\t\t\\\n })\n \n-/* PCIe speed to Mb/s reduced by encoding overhead */\n+/* PCIe speed to Mb/s reduced by encoding overhead:\n+ * Gen 1-2 (2.5, 5 GT/s): 8b/10b encoding\n+ * Gen 3-5 (8, 16, 32 GT/s): 128b/130b encoding\n+ * Gen 6+ (64, 128 GT/s): Flit mode, 1:1 (no encoding overhead)\n+ */\n #define PCIE_SPEED2MBS_ENC(speed) \\\n-\t((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \\\n+\t((speed) == PCIE_SPEED_128_0GT ? 128000*1/1 : \\\n+\t (speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \\\n \t (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \\\n \t (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \\\n \t (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \\\n@@ -544,6 +552,8 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)\n \t\treturn 32000;\n \tcase PCIE_SPEED_64_0GT:\n \t\treturn 64000;\n+\tcase PCIE_SPEED_128_0GT:\n+\t\treturn 128000;\n \tdefault:\n \t\tbreak;\n \t}\n@@ -551,7 +561,13 @@ static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)\n \treturn -EINVAL;\n }\n \n-u8 pcie_get_supported_speeds(struct pci_dev *dev);\n+/* PCIe Gen 6+ (>= 64 GT/s) requires Flit mode with 1:1 encoding */\n+static inline bool pcie_speed_requires_flit(enum pci_bus_speed speed)\n+{\n+\treturn speed >= PCIE_SPEED_64_0GT && speed <= PCIE_SPEED_128_0GT;\n+}\n+\n+u16 pcie_get_supported_speeds(struct pci_dev *dev);\n const char *pci_speed_string(enum pci_bus_speed speed);\n void __pcie_print_link_status(struct pci_dev *dev, bool verbose);\n void pcie_report_downtraining(struct pci_dev *dev);\ndiff --git a/drivers/pci/probe.c b/drivers/pci/probe.c\nindex 9d4eeda5ea946..031c3ec8615d2 100644\n--- a/drivers/pci/probe.c\n+++ b/drivers/pci/probe.c\n@@ -774,7 +774,7 @@ const unsigned char pcie_link_speed[] = {\n \tPCIE_SPEED_16_0GT,\t\t/* 4 */\n \tPCIE_SPEED_32_0GT,\t\t/* 5 */\n \tPCIE_SPEED_64_0GT,\t\t/* 6 */\n-\tPCI_SPEED_UNKNOWN,\t\t/* 7 */\n+\tPCIE_SPEED_128_0GT,\t\t/* 7 */\n \tPCI_SPEED_UNKNOWN,\t\t/* 8 */\n \tPCI_SPEED_UNKNOWN,\t\t/* 9 */\n \tPCI_SPEED_UNKNOWN,\t\t/* A */\n@@ -816,6 +816,7 @@ const char *pci_speed_string(enum pci_bus_speed speed)\n \t \"16.0 GT/s PCIe\",\t\t/* 0x17 */\n \t \"32.0 GT/s PCIe\",\t\t/* 0x18 */\n \t \"64.0 GT/s PCIe\",\t\t/* 0x19 */\n+\t \"128.0 GT/s PCIe\",\t\t/* 0x1a */\n \t};\n \n \tif (speed < ARRAY_SIZE(speed_strings))\n", "prefixes": [ "RFC", "2/3" ] }