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GET /api/patches/2197113/?format=api
{ "id": 2197113, "url": "http://patchwork.ozlabs.org/api/patches/2197113/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217-master-v1-2-727e26cdfaf5@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217-master-v1-2-727e26cdfaf5@nvidia.com>", "list_archive_url": null, "date": "2026-02-17T05:54:42", "name": "[2/4] PCI: tegra194: Use 64-bit BAR layout and reset only first BAR in EP mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5b3e1410d8d1afbec32339ebbcb771cb9278e7dc", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217-master-v1-2-727e26cdfaf5@nvidia.com/mbox/", "series": [ { "id": 492374, "url": "http://patchwork.ozlabs.org/api/series/492374/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492374", "date": "2026-02-17T05:54:40", "name": "PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492374/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197113/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197113/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47412-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=MTlC9TV5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "Niklas Cassel <cassel@kernel.org>, Vidya Sagar <vidyas@nvidia.com>,\n Manivannan Sadhasivam <mani@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84sk?=\n\t=?utf-8?q?i?= <kwilczynski@kernel.org>,\n \"Kishon Vijay Abraham I\" <kishon@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n \"Lorenzo Pieralisi\" <lpieralisi@kernel.org>, Rob Herring <robh@kernel.org>,\n \"Thierry Reding\" <thierry.reding@gmail.com>,\n Jonathan Hunter <jonathanh@nvidia.com>, Arnd Bergmann <arnd@arndb.de>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n Masami Hiramatsu <mhiramat@kernel.org>", "CC": "Manikanta Maddireddy <mmaddireddy@nvidia.com>,\n\t<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH 2/4] PCI: tegra194: Use 64-bit BAR layout and reset only first\n BAR in EP mode", "Date": "Tue, 17 Feb 2026 11:24:42 +0530", "Message-ID": "<20260217-master-v1-2-727e26cdfaf5@nvidia.com>", "X-Mailer": [ "git-send-email 2.34.1", "b4 0.14.3" ], "In-Reply-To": "<20260217-master-v1-0-727e26cdfaf5@nvidia.com>", "References": "<20260217-master-v1-0-727e26cdfaf5@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; 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Do not\nreset BAR2+BAR3 or BAR4+BAR5 so that MSI-X and DMA remain enabled for\nthe host.\n\nThis keeps CONSECUTIVE_BAR_TEST and DMA tests working while allowing\nthe host to use 64-bit BAR 2 (MSI-X) and 64-bit BAR 4 (DMA) for real\nuse.\n\nBAR0 is capabale of supporting various sizes using DBI2 BAR registers\nwhich are programmed in dw_pcie_ep_set_bar_programmable(), remove\n1 MB size limit from pci_epc_features.\n\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\n drivers/pci/controller/dwc/pcie-tegra194.c | 26 +++++++++++++++-----------\n 1 file changed, 15 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c\nindex 1b4fc6a9bed1..6734d1336ef1 100644\n--- a/drivers/pci/controller/dwc/pcie-tegra194.c\n+++ b/drivers/pci/controller/dwc/pcie-tegra194.c\n@@ -1948,11 +1948,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)\n static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)\n {\n \tstruct dw_pcie *pci = to_dw_pcie_from_ep(ep);\n-\tenum pci_barno bar;\n \n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tdw_pcie_ep_reset_bar(pci, bar);\n-};\n+\t/*\n+\t * Only reset the first 64-bit BAR (BAR0+BAR1); EPF will enable it via set_bar.\n+\t * BAR2+BAR3 (MSI-X table) and BAR4+BAR5 (DMA regs) are HW-backed and must\n+\t * stay enabled.\n+\t */\n+\tdw_pcie_ep_reset_bar(pci, BAR_0);\n+\tdw_pcie_ep_reset_bar(pci, BAR_1);\n+}\n \n static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)\n {\n@@ -2009,16 +2013,16 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,\n \treturn 0;\n }\n \n+/* Tegra194 EP: BAR0 = programmable BAR, BAR2 = MSI-X table, BAR4 = DMA regs. */\n static const struct pci_epc_features tegra_pcie_epc_features = {\n \t.linkup_notifier = true,\n \t.msi_capable = true,\n-\t.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,\n-\t\t\t.only_64bit = true, },\n-\t.bar[BAR_1] = { .type = BAR_RESERVED, },\n-\t.bar[BAR_2] = { .type = BAR_RESERVED, },\n-\t.bar[BAR_3] = { .type = BAR_RESERVED, },\n-\t.bar[BAR_4] = { .type = BAR_RESERVED, },\n-\t.bar[BAR_5] = { .type = BAR_RESERVED, },\n+\t.bar[BAR_0] = { .type = BAR_PROGRAMMABLE, .only_64bit = true, },\n+\t.bar[BAR_1] = { .type = BAR_RESERVED, },\t/* high half of 64-bit BAR0 */\n+\t.bar[BAR_2] = { .type = BAR_RESERVED, .only_64bit = true, },\t/* MSI-X table */\n+\t.bar[BAR_3] = { .type = BAR_RESERVED, },\t/* high half of 64-bit BAR2 */\n+\t.bar[BAR_4] = { .type = BAR_RESERVED, .only_64bit = true, },\t/* DMA regs */\n+\t.bar[BAR_5] = { .type = BAR_RESERVED, },\t/* high half of 64-bit BAR4 */\n \t.align = SZ_64K,\n };\n \n", "prefixes": [ "2/4" ] }