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GET /api/patches/2197111/?format=api
{ "id": 2197111, "url": "http://patchwork.ozlabs.org/api/patches/2197111/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217-master-v1-3-727e26cdfaf5@nvidia.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217-master-v1-3-727e26cdfaf5@nvidia.com>", "list_archive_url": null, "date": "2026-02-17T05:54:43", "name": "[3/4] misc: pci_endpoint_test: Add BAR skip mask and NVIDIA Tegra EP device IDs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "86ab9edd4d524f2f56d51e5827a6c2d9c77c111e", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260217-master-v1-3-727e26cdfaf5@nvidia.com/mbox/", "series": [ { "id": 492374, "url": "http://patchwork.ozlabs.org/api/series/492374/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=492374", "date": "2026-02-17T05:54:40", "name": "PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492374/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197111/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197111/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-47411-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Amb/BFR/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "Niklas Cassel <cassel@kernel.org>, Vidya Sagar <vidyas@nvidia.com>,\n Manivannan Sadhasivam <mani@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84sk?=\n\t=?utf-8?q?i?= <kwilczynski@kernel.org>,\n \"Kishon Vijay Abraham I\" <kishon@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n \"Lorenzo Pieralisi\" <lpieralisi@kernel.org>, Rob Herring <robh@kernel.org>,\n \"Thierry Reding\" <thierry.reding@gmail.com>,\n Jonathan Hunter <jonathanh@nvidia.com>, Arnd Bergmann <arnd@arndb.de>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n Masami Hiramatsu <mhiramat@kernel.org>", "CC": "Manikanta Maddireddy <mmaddireddy@nvidia.com>,\n\t<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH 3/4] misc: pci_endpoint_test: Add BAR skip mask and NVIDIA\n Tegra EP device IDs", "Date": "Tue, 17 Feb 2026 11:24:43 +0530", "Message-ID": "<20260217-master-v1-3-727e26cdfaf5@nvidia.com>", "X-Mailer": [ "git-send-email 2.34.1", "b4 0.14.3" ], "In-Reply-To": "<20260217-master-v1-0-727e26cdfaf5@nvidia.com>", "References": "<20260217-master-v1-0-727e26cdfaf5@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; 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When a BAR is\nskipped, it is not written or read in the consecutive BAR test, and\nPCITEST_BAR ioctl for that BAR returns -EINVAL.\n\nAdd Tegra endpoint test data with bar_skip_mask set to skip BAR1\nthrough BAR5 (test only BAR0, the first 64-bit BAR). Add\npci_endpoint_test_tbl entries for NVIDIA Tegra194 EP (device ID\n0x1AD4) and Tegra234 EP (device ID 0x229B) so the host test driver\ncan bind and run tests without corrupting MSI-X or DMA registers.\n\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\n drivers/misc/pci_endpoint_test.c | 34 +++++++++++++++++++++++++++++++---\n 1 file changed, 31 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c\nindex 1c0fd185114f..4c9f02dbc41b 100644\n--- a/drivers/misc/pci_endpoint_test.c\n+++ b/drivers/misc/pci_endpoint_test.c\n@@ -100,6 +100,12 @@\n \n #define PCI_DEVICE_ID_ROCKCHIP_RK3588\t\t0x3588\n \n+#define PCI_DEVICE_ID_NVIDIA_TEGRA194_EP\t0x1ad4\n+#define PCI_DEVICE_ID_NVIDIA_TEGRA234_EP\t0x229b\n+\n+/* BARs 1-5 are HW-backed (MSI-X, DMA) or high half of 64-bit BAR0; skip BAR test */\n+#define TEGRA_EP_BAR_SKIP_MASK\t(BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5))\n+\n static DEFINE_IDA(pci_endpoint_test_ida);\n \n #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \\\n@@ -130,11 +136,15 @@ struct pci_endpoint_test {\n \tsize_t alignment;\n \tu32 ep_caps;\n \tconst char *name;\n+\t/* Bitmask of BARs to skip in BAR test (bit N set = skip BAR N) */\n+\tu8 bar_skip_mask;\n };\n \n struct pci_endpoint_test_data {\n \tenum pci_barno test_reg_bar;\n \tsize_t alignment;\n+\t/* Bitmask of BARs to skip in BAR test (bit N set = skip BAR N) */\n+\tu8 bar_skip_mask;\n };\n \n static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,\n@@ -393,9 +403,10 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)\n \tint ret;\n \n \t/* Write all BARs in order (without reading). */\n-\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++)\n-\t\tif (test->bar[bar])\n+\tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {\n+\t\tif (test->bar[bar] && !(test->bar_skip_mask & (1 << bar)))\n \t\t\tpci_endpoint_test_bars_write_bar(test, bar);\n+\t}\n \n \t/*\n \t * Read all BARs in order (without writing).\n@@ -404,7 +415,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)\n \t * (Reading back the BAR directly after writing can not detect this.)\n \t */\n \tfor (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {\n-\t\tif (test->bar[bar]) {\n+\t\tif (test->bar[bar] && !(test->bar_skip_mask & (1 << bar))) {\n \t\t\tret = pci_endpoint_test_bars_read_bar(test, bar);\n \t\t\tif (ret)\n \t\t\t\treturn ret;\n@@ -941,6 +952,10 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,\n \t\t\tgoto ret;\n \t\tif (is_am654_pci_dev(pdev) && bar == BAR_0)\n \t\t\tgoto ret;\n+\t\tif (test->bar_skip_mask & (1 << bar)) {\n+\t\t\tret = 0;\n+\t\t\tgoto ret;\n+\t\t}\n \t\tret = pci_endpoint_test_bar(test, bar);\n \t\tbreak;\n \tcase PCITEST_BARS:\n@@ -1028,6 +1043,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev,\n \t\ttest_reg_bar = data->test_reg_bar;\n \t\ttest->test_reg_bar = test_reg_bar;\n \t\ttest->alignment = data->alignment;\n+\t\ttest->bar_skip_mask = data->bar_skip_mask;\n \t}\n \n \tinit_completion(&test->irq_raised);\n@@ -1173,6 +1189,12 @@ static const struct pci_endpoint_test_data rk3588_data = {\n \t.alignment = SZ_64K,\n };\n \n+static const struct pci_endpoint_test_data tegra_ep_data = {\n+\t.test_reg_bar = BAR_0,\n+\t.alignment = SZ_64K,\n+\t.bar_skip_mask = TEGRA_EP_BAR_SKIP_MASK,\n+};\n+\n /*\n * If the controller's Vendor/Device ID are programmable, you may be able to\n * use one of the existing entries for testing instead of adding a new one.\n@@ -1217,6 +1239,12 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {\n \t{ PCI_DEVICE(PCI_VENDOR_ID_ROCKCHIP, PCI_DEVICE_ID_ROCKCHIP_RK3588),\n \t .driver_data = (kernel_ulong_t)&rk3588_data,\n \t},\n+\t{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA194_EP),\n+\t .driver_data = (kernel_ulong_t)&tegra_ep_data,\n+\t},\n+\t{ PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TEGRA234_EP),\n+\t .driver_data = (kernel_ulong_t)&tegra_ep_data,\n+\t},\n \t{ }\n };\n MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);\n", "prefixes": [ "3/4" ] }