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GET /api/patches/2197108/?format=api
{ "id": 2197108, "url": "http://patchwork.ozlabs.org/api/patches/2197108/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260217-master-v1-1-727e26cdfaf5@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260217-master-v1-1-727e26cdfaf5@nvidia.com>", "list_archive_url": null, "date": "2026-02-17T05:54:41", "name": "[1/4] PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED semantics", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f9388c585ffa179dfa679b13a05ab66ee5688ebd", "submitter": { "id": 72399, "url": "http://patchwork.ozlabs.org/api/people/72399/?format=api", "name": "Manikanta Maddireddy", "email": "mmaddireddy@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260217-master-v1-1-727e26cdfaf5@nvidia.com/mbox/", "series": [ { "id": 492373, "url": "http://patchwork.ozlabs.org/api/series/492373/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=492373", "date": "2026-02-17T05:54:40", "name": "PCI: endpoint: Add BAR_DISABLED support to PCI endpoint framework", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492373/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197108/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197108/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-11968-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": 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216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Manikanta Maddireddy <mmaddireddy@nvidia.com>", "To": "Niklas Cassel <cassel@kernel.org>, Vidya Sagar <vidyas@nvidia.com>,\n Manivannan Sadhasivam <mani@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84sk?=\n\t=?utf-8?q?i?= <kwilczynski@kernel.org>,\n \"Kishon Vijay Abraham I\" <kishon@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n \"Lorenzo Pieralisi\" <lpieralisi@kernel.org>, Rob Herring <robh@kernel.org>,\n \"Thierry Reding\" <thierry.reding@gmail.com>,\n Jonathan Hunter <jonathanh@nvidia.com>, Arnd Bergmann <arnd@arndb.de>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,\n Masami Hiramatsu <mhiramat@kernel.org>", "CC": "Manikanta Maddireddy <mmaddireddy@nvidia.com>,\n\t<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>", "Subject": "[PATCH 1/4] PCI: endpoint: Add BAR_DISABLED and document BAR_RESERVED\n semantics", "Date": "Tue, 17 Feb 2026 11:24:41 +0530", "Message-ID": "<20260217-master-v1-1-727e26cdfaf5@nvidia.com>", "X-Mailer": [ "git-send-email 2.34.1", "b4 0.14.3" ], "In-Reply-To": "<20260217-master-v1-0-727e26cdfaf5@nvidia.com>", "References": "<20260217-master-v1-0-727e26cdfaf5@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", 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"=?utf-8?q?Iw7oO5w2VfDwBYIa9NqFyZvFM5zKJnW?=\n\t=?utf-8?q?d+dQw2qC6M5ldlZQinfYTV5tWQiYUHTK1sp4GJEMUtoVSt34lANU5sJcHYVMwbMek?=\n\t=?utf-8?q?hIXA5uiP53W+7QeiPk8DFpCpOIx6l6/TtMNjI0dQl5rGVZW7esyFtXDTGpK0xMn7y?=\n\t=?utf-8?q?oxcXm0Ar4DccuBoPRSyKZQ3rl8COEb9wD+h+LCEBvSVOaO7JxtbmChwsCkEhh3V5N?=\n\t=?utf-8?q?+BYomrJjpBSEmna9ZGPiDv3nX+hSidJCdx0ROWrJxz2OnAk4MmekX7SyxKZrXs3Xb?=\n\t=?utf-8?q?U4MJ7YoA6EBXwLDDMyW4WMEk7jODue+5JT+gFrLByTO5jtUQCPz2kwDx/XTLpHkEy?=\n\t=?utf-8?q?ocJfoMHZx1xKOd2nBuat5PYqtzn+hTdaWG0y7Iq+7F+G5Nu2UB76rM6yLgtes6zRn?=\n\t=?utf-8?q?9SxoRJmXQUefnoxAohvTRDw67tEsV6uwh5WAjU3iSkCmy7ZjgV6x4JnKM9nvuZZG7?=\n\t=?utf-8?q?UL7QJPuzOMGG9lgjdnzzdH2l9QaxHWYvAYSoqBsmN6FSgEKgd6UaJu+3+bbp2qmk/?=\n\t=?utf-8?q?YL2MbMjB41vNwV2Ip/C3K3nQUzN5NinOedTvRTyE9IjLdJnz3shYa2fLiGii+q72Z?=\n\t=?utf-8?q?LM+fn3rIW2NcSua+h6OeTixikKUjtbvvAZaV9Xc3vdh02Ju8FYG6FgFVWHOkdhuWY?=\n\t=?utf-8?q?VixXjH295aHRaYsdOVgTi7dXFctiwehv0eynxuN+VU5yGhn/XT2+8YeqL+gxFg3zx?=\n\t=?utf-8?q?hBYkzeDY53wVtVKEOPKDhgm6E/P84Iy/5o6bhFHr5RXAqvkbPo/MLj6rs7Qg5eaG3?=\n\t=?utf-8?q?JnACmVvvH3wejvoNFl7VMaVwcy7xL/B9D34Un5+yNEO3nbgH8OBBegqfLSLz5Q3+x?=\n\t=?utf-8?q?PQX8IlOBr9XK3CRWz4nylHvPNSPl6sXq9v6E3lPaBarKRmT/Vdrow+KSqOHBwoWC1?=\n\t=?utf-8?q?ORnXBpQkQN5UNckqhr/35Vvp16qZA7uxGqBh5Td60Am+oX5HkFMh9YUoUUt7d2Ffc?=\n\t=?utf-8?q?+VqoUzw/tBLYLMYMa6AJta6mjUR6GA09JFpYycWQQvCQiygTPrv7lsERIkyA/g9oj?=\n\t=?utf-8?q?/Fz78ArQHOHRhm/i0bkNwfYhIRt2Khv9r7uKXPHiwnGR1FesV0WJ2yvCxBaiZLfDi?=\n\t=?utf-8?q?dACwpjZTNL2RWm/+/D7nC5f/TPKaQ6jOiy0OpJGU1Rd4mn2tRTbtNJ0rnkSAChMEY?=\n\t=?utf-8?q?fYKtKw59nZlqQ663TZZouGu3B0RHH3gwOuH8C2vrdY8IS2HwYU4fAX2fAGj6TG2ez?=\n\t=?utf-8?q?qJ3vTynvQMWyN1qb9sikdkj4ZUu+WrfbnD2vauIMEScKrHm8zejwVpaWc3k27pUvm?=\n\t=?utf-8?q?gwW7w2nbC5cltgq42mQoIvdT/X9tbuMi/A0ZTi7laDlhAVPwL94+m8w4N/Vu3O0L/?=\n\t=?utf-8?q?J5gwREBg2Tjko61bsnGOY9pRFKuDoN/ekLsjBTrSRj8qFgVexJAwYF9g6D3I60e/i?=\n\t=?utf-8?q?WMbc5jQohq8W5prvXO0l5nPAK1kOqi5DLFf+mEnIi+/kFsUKXxvN/4UaH1CQG7eMr?=\n\t=?utf-8?q?8/yiTLe9+mZGkbc2eO4GlgwZUo3C1vSd4Ygayfha+L8hdhraWc561JnO1J+jLH/85?=\n\t=?utf-8?q?oAVFgq/tInMgg6NAvJV2JN2cuqbt6WfPGOZjCggjvfNHa/MGl6Be6+5R3MwF9QLPI?=\n\t=?utf-8?q?5Q3ktTAx68K1nYuGwK8EhsjZj+AUfrRcNr917+6FjxD38gQX/RA=3D?=", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013)(7416014)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tJ2QGteh8Gx8lkmM4P0BLWy/sqWpC1T2Z/xs4EsvG2iy6b2aQl8/Gq7ktTL6QCOizPJTkqQNGTcGghdzfINBkE55+xz6Hf8QLG7RNeD+kHN5awZlpdIPbwOmbdF2jx8hKn88tc1ovzqlOE2L4k1X3ncB7bXJ3PAUlMCThCWn4IeHKDsLQKnWJEY2gF+GEa1zN9vf2L8dLiqsjEpUV2tT9tcdW9xLrqBkLDcj54bwByzkJvud5ktg1J4fQEqSooI1Dh6w4znwM2gqCGIUzRTfCcUUd1QDvUHZQRPIZF5utvvVBkZHkrYLQiJjQVnVka0bh92Y+r9owdM/nWb8EXQ+eI4CTrcGkkjPv0CaTvl5j3SKdMtKmgnkznu3Ufdw8b+OCQY8FPeooEkAkpqxfMP2CHYhLxQG+DEZExTGoli98ujuiveZqxS1Mc0mJoaNgAo2n", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Feb 2026 05:55:40.7944\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 48b38a5f-61ea-40d9-1779-08de6de92e92", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDS3PEPF0000C37C.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB7886" }, "content": "Add BAR_DISABLED to enum pci_epc_bar_type for BARs that are unused: the\nEPC must disable them in .init(), the EPF must not use them, and they\nare not returned by pci_epc_get_next_free_bar().\n\nDocument BAR_RESERVED for two uses: (1) HW-backed BARs (e.g. MSI-X\ntable, DMA regs) that the EPC may leave enabled for the host, and\n(2) the second register of a 64-bit BAR (high 32 bits) when the\npreceding BAR has only_64bit set.\n\nUpdate pci_epc_get_next_free_bar() to treat both BAR_RESERVED and\nBAR_DISABLED as not free so EPF drivers do not allocate or use\nthese BARs.\n\nThis allows EPC drivers such as Tegra194 to keep HW-backed 64-bit\nBARs (MSI-X, DMA) enabled while still preventing EPF from using\nreserved or disabled BARs.\n\nSigned-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>\n---\n drivers/pci/endpoint/pci-epc-core.c | 5 +++--\n include/linux/pci-epc.h | 13 +++++++++++--\n 2 files changed, 14 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c\nindex ca7f19cc973a..1d6b04ac4fc5 100644\n--- a/drivers/pci/endpoint/pci-epc-core.c\n+++ b/drivers/pci/endpoint/pci-epc-core.c\n@@ -103,8 +103,9 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features\n \t\tbar++;\n \n \tfor (i = bar; i < PCI_STD_NUM_BARS; i++) {\n-\t\t/* If the BAR is not reserved, return it. */\n-\t\tif (epc_features->bar[i].type != BAR_RESERVED)\n+\t\t/* If the BAR is not reserved or disabled, return it. */\n+\t\tif (epc_features->bar[i].type != BAR_RESERVED &&\n+\t\t epc_features->bar[i].type != BAR_DISABLED)\n \t\t\treturn i;\n \t}\n \ndiff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h\nindex 4286bfdbfdfa..9b3714a0dafc 100644\n--- a/include/linux/pci-epc.h\n+++ b/include/linux/pci-epc.h\n@@ -191,13 +191,21 @@ struct pci_epc {\n * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.\n *\t\t NOTE: An EPC driver can currently only set a single supported\n *\t\t size.\n- * @BAR_RESERVED: The BAR should not be touched by an EPF driver.\n+ * @BAR_RESERVED: The BAR should not be touched by an EPF driver. Used for:\n+ *\t\t (1) HW-backed BARs (e.g. MSI-X table, DMA regs) that the EPC\n+ *\t\t may leave enabled for the host; (2) the second register\n+ *\t\t of a 64-bit BAR (the high 32 bits), when the preceding\n+ *\t\t BAR has only_64bit set.\n+ * @BAR_DISABLED: The BAR is unused; the EPC must disable it in .init(); the\n+ *\t\t EPF must not use it; it is not returned by\n+ *\t\t pci_epc_get_next_free_bar().\n */\n enum pci_epc_bar_type {\n \tBAR_PROGRAMMABLE = 0,\n \tBAR_FIXED,\n \tBAR_RESIZABLE,\n \tBAR_RESERVED,\n+\tBAR_DISABLED,\n };\n \n /**\n@@ -212,7 +220,8 @@ enum pci_epc_bar_type {\n *\t\tonly_64bit should not be set on a BAR of type BAR_RESERVED.\n *\t\t(If BARx is a 64-bit BAR that an EPF driver is not allowed to\n *\t\ttouch, then both BARx and BARx+1 must be set to type\n- *\t\tBAR_RESERVED.)\n+ *\t\tBAR_RESERVED. BAR_RESERVED is used both for HW-backed BARs and\n+ *\t\tfor the high half of a 64-bit BAR.)\n */\n struct pci_epc_bar_desc {\n \tenum pci_epc_bar_type type;\n", "prefixes": [ "1/4" ] }