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GET /api/patches/2197075/?format=api
{ "id": 2197075, "url": "http://patchwork.ozlabs.org/api/patches/2197075/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260216225228.53959-4-philmd@linaro.org/", "project": { "id": 69, "url": "http://patchwork.ozlabs.org/api/projects/69/?format=api", "name": "QEMU powerpc development", "link_name": "qemu-ppc", "list_id": "qemu-ppc.nongnu.org", "list_email": "qemu-ppc@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216225228.53959-4-philmd@linaro.org>", "list_archive_url": null, "date": "2026-02-16T22:52:19", "name": "[03/11] target/sparc: Restore 'gdb-xml/sparc64-fpu.xml'", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4689b2b6e6782d8fce7871c51796c2c8664862d3", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260216225228.53959-4-philmd@linaro.org/mbox/", "series": [ { "id": 492360, "url": "http://patchwork.ozlabs.org/api/series/492360/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-ppc/list/?series=492360", "date": "2026-02-16T22:52:16", "name": "monitor/hmp: Automatically handle gdb-xml exposed registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492360/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197075/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197075/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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<gustavo.romero@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>, unisono@quyllur.org, =?utf-8?q?Philipp?=\n\t=?utf-8?q?e_Mathieu-Daud=C3=A9?= <philmd@linaro.org>, qemu-ppc@nongnu.org", "Subject": "[PATCH 03/11] target/sparc: Restore 'gdb-xml/sparc64-fpu.xml'", "Date": "Mon, 16 Feb 2026 23:52:19 +0100", "Message-ID": "<20260216225228.53959-4-philmd@linaro.org>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20260216225228.53959-1-philmd@linaro.org>", "References": "<20260216225228.53959-1-philmd@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::343;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x343.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-ppc@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-ppc.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-ppc>", "List-Post": "<mailto:qemu-ppc@nongnu.org>", "List-Help": "<mailto:qemu-ppc-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Restore gdb-xml/sparc64-fpu.xml from mainstream binutils, tag\n'binutils-2_46', found in the gdb/features/sparc/folder [*].\n\nExtract sparc_fpu_gdb_write_register() out of\nsparc_cpu_gdb_read_register() and sparc_fpu_gdb_write_register()\nout of sparc_cpu_gdb_write_register(), taking care to update the\nregister indexes in the switch cases.\n\nRegister these helpers with a call to gdb_register_coprocessor()\nin sparc_cpu_register_gdb_regs().\n\n[*] https://sourceware.org/git/?p=binutils-gdb.git;a=tree;f=gdb/features/sparc;hb=refs/tags/binutils-2_46\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n configs/targets/sparc64-linux-user.mak | 2 +-\n configs/targets/sparc64-softmmu.mak | 2 +-\n target/sparc/cpu.c | 2 +-\n target/sparc/gdbstub.c | 88 +++++++++++++++++---------\n gdb-xml/sparc64-core.xml | 50 ---------------\n gdb-xml/sparc64-fpu.xml | 59 +++++++++++++++++\n 6 files changed, 120 insertions(+), 83 deletions(-)\n create mode 100644 gdb-xml/sparc64-fpu.xml", "diff": "diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc64-linux-user.mak\nindex 930f7e13ab9..a5f8f8d51a2 100644\n--- a/configs/targets/sparc64-linux-user.mak\n+++ b/configs/targets/sparc64-linux-user.mak\n@@ -4,6 +4,6 @@ TARGET_ABI_DIR=sparc\n TARGET_SYSTBL_ABI=common,64\n TARGET_SYSTBL=syscall.tbl\n TARGET_BIG_ENDIAN=y\n-TARGET_XML_FILES=gdb-xml/sparc64-core.xml gdb-xml/sparc64-cp0.xml\n+TARGET_XML_FILES=gdb-xml/sparc64-core.xml gdb-xml/sparc64-fpu.xml gdb-xml/sparc64-cp0.xml\n TARGET_LONG_BITS=64\n TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y\ndiff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak\nindex 22e7f3c94a7..c35b6b1bb8a 100644\n--- a/configs/targets/sparc64-softmmu.mak\n+++ b/configs/targets/sparc64-softmmu.mak\n@@ -1,7 +1,7 @@\n TARGET_ARCH=sparc64\n TARGET_BASE_ARCH=sparc\n TARGET_BIG_ENDIAN=y\n-TARGET_XML_FILES=gdb-xml/sparc64-core.xml gdb-xml/sparc64-cp0.xml\n+TARGET_XML_FILES=gdb-xml/sparc64-core.xml gdb-xml/sparc64-fpu.xml gdb-xml/sparc64-cp0.xml\n TARGET_LONG_BITS=64\n TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y\n TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y\ndiff --git a/target/sparc/cpu.c b/target/sparc/cpu.c\nindex 6f7b250abb3..2db34d88b97 100644\n--- a/target/sparc/cpu.c\n+++ b/target/sparc/cpu.c\n@@ -1094,7 +1094,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)\n \n #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)\n cc->gdb_core_xml_file = \"sparc64-core.xml\";\n- cc->gdb_num_core_regs = 80;\n+ cc->gdb_num_core_regs = 32;\n #else\n cc->gdb_num_core_regs = 72;\n #endif\ndiff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c\nindex bdd759dd0a9..b5b1494950a 100644\n--- a/target/sparc/gdbstub.c\n+++ b/target/sparc/gdbstub.c\n@@ -40,32 +40,40 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n /* register window */\n return gdb_get_rega(mem_buf, env->regwptr[n - 8]);\n }\n+ return 0;\n+}\n+\n+__attribute__((unused))\n+static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n+{\n+ CPUSPARCState *env = cpu_env(cs);\n+\n #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n- if (n < 64) {\n+ if (n < 32) {\n /* fprs */\n if (n & 1) {\n- return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);\n+ return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.lower);\n } else {\n- return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);\n+ return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.upper);\n }\n }\n #else\n- if (n < 64) {\n+ if (n < 32) {\n /* f0-f31 */\n if (n & 1) {\n- return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.lower);\n+ return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.lower);\n } else {\n- return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);\n+ return gdb_get_reg32(mem_buf, env->fpr[n / 2].l.upper);\n }\n }\n- if (n < 80) {\n+ if (n < 48) {\n /* f32-f62 (16 double width registers, even register numbers only)\n- * n == 64: f32 : env->fpr[16]\n- * n == 65: f34 : env->fpr[17]\n+ * n == 32: f32 : env->fpr[16]\n+ * n == 33: f34 : env->fpr[17]\n * etc...\n- * n == 79: f62 : env->fpr[31]\n+ * n == 47: f62 : env->fpr[31]\n */\n- return gdb_get_reg64(mem_buf, env->fpr[(n - 64) + 16].ll);\n+ return gdb_get_reg64(mem_buf, env->fpr[(n - 32) + 16].ll);\n }\n #endif\n return 0;\n@@ -135,39 +143,55 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n if (n < 8) {\n /* g0..g7 */\n env->gregs[n] = tmp;\n- } else if (n < 32) {\n+ } else {\n /* register window */\n env->regwptr[n - 8] = tmp;\n }\n #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n- else if (n < 64) {\n- /* fprs */\n- /* f0-f31 */\n- if (n & 1) {\n- env->fpr[(n - 32) / 2].l.lower = tmp;\n- } else {\n- env->fpr[(n - 32) / 2].l.upper = tmp;\n- }\n- }\n return 4;\n #else\n- else if (n < 64) {\n+ return 8;\n+#endif\n+}\n+\n+__attribute__((unused))\n+static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n+{\n+ CPUSPARCState *env = cpu_env(cs);\n+\n+#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n+ uint32_t tmp;\n+\n+ tmp = ldl_p(mem_buf);\n+\n+ /* fprs */\n+ /* f0-f31 */\n+ if (n & 1) {\n+ env->fpr[n / 2].l.lower = tmp;\n+ } else {\n+ env->fpr[n / 2].l.upper = tmp;\n+ }\n+\n+ return 4;\n+#else\n+ if (n < 32) {\n /* f0-f31 */\n- tmp = ldl_p(mem_buf);\n+ uint32_t tmp = ldl_p(mem_buf);\n if (n & 1) {\n- env->fpr[(n - 32) / 2].l.lower = tmp;\n+ env->fpr[n / 2].l.lower = tmp;\n } else {\n- env->fpr[(n - 32) / 2].l.upper = tmp;\n+ env->fpr[n / 2].l.upper = tmp;\n }\n return 4;\n- } else if (n < 80) {\n+ } else {\n+ uint64_t tmp = ldq_p(mem_buf);\n /* f32-f62 (16 double width registers, even register numbers only)\n- * n == 64: f32 : env->fpr[16]\n- * n == 65: f34 : env->fpr[17]\n+ * n == 32: f32 : env->fpr[16]\n+ * n == 33: f34 : env->fpr[17]\n * etc...\n- * n == 79: f62 : env->fpr[31]\n+ * n == 47: f62 : env->fpr[31]\n */\n- env->fpr[(n - 64) + 16].ll = tmp;\n+ env->fpr[(n - 32) + 16].ll = tmp;\n }\n return 8;\n #endif\n@@ -249,6 +273,10 @@ void sparc_cpu_register_gdb_regs(CPUState *cs)\n #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n /* Not yet supported */\n #else\n+ gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,\n+ sparc_fpu_gdb_write_register,\n+ gdb_find_static_feature(\"sparc64-fpu.xml\"),\n+ 0);\n gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,\n sparc_cp0_gdb_write_register,\n gdb_find_static_feature(\"sparc64-cp0.xml\"),\ndiff --git a/gdb-xml/sparc64-core.xml b/gdb-xml/sparc64-core.xml\nindex 1c26d8c01c1..85b0820a408 100644\n--- a/gdb-xml/sparc64-core.xml\n+++ b/gdb-xml/sparc64-core.xml\n@@ -39,54 +39,4 @@\n <reg name=\"i5\" bitsize=\"64\" type=\"uint64\" regnum=\"29\"/>\n <reg name=\"fp\" bitsize=\"64\" type=\"uint64\" regnum=\"30\"/>\n <reg name=\"i7\" bitsize=\"64\" type=\"uint64\" regnum=\"31\"/>\n-\n- <reg name=\"f0\" bitsize=\"32\" type=\"ieee_single\" regnum=\"32\"/>\n- <reg name=\"f1\" bitsize=\"32\" type=\"ieee_single\" regnum=\"33\"/>\n- <reg name=\"f2\" bitsize=\"32\" type=\"ieee_single\" regnum=\"34\"/>\n- <reg name=\"f3\" bitsize=\"32\" type=\"ieee_single\" regnum=\"35\"/>\n- <reg name=\"f4\" bitsize=\"32\" type=\"ieee_single\" regnum=\"36\"/>\n- <reg name=\"f5\" bitsize=\"32\" type=\"ieee_single\" regnum=\"37\"/>\n- <reg name=\"f6\" bitsize=\"32\" type=\"ieee_single\" regnum=\"38\"/>\n- <reg name=\"f7\" bitsize=\"32\" type=\"ieee_single\" regnum=\"39\"/>\n- <reg name=\"f8\" bitsize=\"32\" type=\"ieee_single\" regnum=\"40\"/>\n- <reg name=\"f9\" bitsize=\"32\" type=\"ieee_single\" regnum=\"41\"/>\n- <reg name=\"f10\" bitsize=\"32\" type=\"ieee_single\" regnum=\"42\"/>\n- <reg name=\"f11\" bitsize=\"32\" type=\"ieee_single\" regnum=\"43\"/>\n- <reg name=\"f12\" bitsize=\"32\" type=\"ieee_single\" regnum=\"44\"/>\n- <reg name=\"f13\" bitsize=\"32\" type=\"ieee_single\" regnum=\"45\"/>\n- <reg name=\"f14\" bitsize=\"32\" type=\"ieee_single\" regnum=\"46\"/>\n- <reg name=\"f15\" bitsize=\"32\" type=\"ieee_single\" regnum=\"47\"/>\n- <reg name=\"f16\" bitsize=\"32\" type=\"ieee_single\" regnum=\"48\"/>\n- <reg name=\"f17\" bitsize=\"32\" type=\"ieee_single\" regnum=\"49\"/>\n- <reg name=\"f18\" bitsize=\"32\" type=\"ieee_single\" regnum=\"50\"/>\n- <reg name=\"f19\" bitsize=\"32\" type=\"ieee_single\" regnum=\"51\"/>\n- <reg name=\"f20\" bitsize=\"32\" type=\"ieee_single\" regnum=\"52\"/>\n- <reg name=\"f21\" bitsize=\"32\" type=\"ieee_single\" regnum=\"53\"/>\n- <reg name=\"f22\" bitsize=\"32\" type=\"ieee_single\" regnum=\"54\"/>\n- <reg name=\"f23\" bitsize=\"32\" type=\"ieee_single\" regnum=\"55\"/>\n- <reg name=\"f24\" bitsize=\"32\" type=\"ieee_single\" regnum=\"56\"/>\n- <reg name=\"f25\" bitsize=\"32\" type=\"ieee_single\" regnum=\"57\"/>\n- <reg name=\"f26\" bitsize=\"32\" type=\"ieee_single\" regnum=\"58\"/>\n- <reg name=\"f27\" bitsize=\"32\" type=\"ieee_single\" regnum=\"59\"/>\n- <reg name=\"f28\" bitsize=\"32\" type=\"ieee_single\" regnum=\"60\"/>\n- <reg name=\"f29\" bitsize=\"32\" type=\"ieee_single\" regnum=\"61\"/>\n- <reg name=\"f30\" bitsize=\"32\" type=\"ieee_single\" regnum=\"62\"/>\n- <reg name=\"f31\" bitsize=\"32\" type=\"ieee_single\" regnum=\"63\"/>\n-\n- <reg name=\"f32\" bitsize=\"64\" type=\"ieee_double\" regnum=\"64\"/>\n- <reg name=\"f34\" bitsize=\"64\" type=\"ieee_double\" regnum=\"65\"/>\n- <reg name=\"f36\" bitsize=\"64\" type=\"ieee_double\" regnum=\"66\"/>\n- <reg name=\"f38\" bitsize=\"64\" type=\"ieee_double\" regnum=\"67\"/>\n- <reg name=\"f40\" bitsize=\"64\" type=\"ieee_double\" regnum=\"68\"/>\n- <reg name=\"f42\" bitsize=\"64\" type=\"ieee_double\" regnum=\"69\"/>\n- <reg name=\"f44\" bitsize=\"64\" type=\"ieee_double\" regnum=\"70\"/>\n- <reg name=\"f46\" bitsize=\"64\" type=\"ieee_double\" regnum=\"71\"/>\n- <reg name=\"f48\" bitsize=\"64\" type=\"ieee_double\" regnum=\"72\"/>\n- <reg name=\"f50\" bitsize=\"64\" type=\"ieee_double\" regnum=\"73\"/>\n- <reg name=\"f52\" bitsize=\"64\" type=\"ieee_double\" regnum=\"74\"/>\n- <reg name=\"f54\" bitsize=\"64\" type=\"ieee_double\" regnum=\"75\"/>\n- <reg name=\"f56\" bitsize=\"64\" type=\"ieee_double\" regnum=\"76\"/>\n- <reg name=\"f58\" bitsize=\"64\" type=\"ieee_double\" regnum=\"77\"/>\n- <reg name=\"f60\" bitsize=\"64\" type=\"ieee_double\" regnum=\"78\"/>\n- <reg name=\"f62\" bitsize=\"64\" type=\"ieee_double\" regnum=\"79\"/>\n </feature>\ndiff --git a/gdb-xml/sparc64-fpu.xml b/gdb-xml/sparc64-fpu.xml\nnew file mode 100644\nindex 00000000000..d7151b34c7f\n--- /dev/null\n+++ b/gdb-xml/sparc64-fpu.xml\n@@ -0,0 +1,59 @@\n+<?xml version=\"1.0\"?>\n+<!-- Copyright (C) 2013-2026 Free Software Foundation, Inc.\n+\n+ Copying and distribution of this file, with or without modification,\n+ are permitted in any medium without royalty provided the copyright\n+ notice and this notice are preserved. -->\n+\n+<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">\n+<feature name=\"org.gnu.gdb.sparc.fpu\">\n+ <reg name=\"f0\" bitsize=\"32\" type=\"ieee_single\" regnum=\"32\"/>\n+ <reg name=\"f1\" bitsize=\"32\" type=\"ieee_single\" regnum=\"33\"/>\n+ <reg name=\"f2\" bitsize=\"32\" type=\"ieee_single\" regnum=\"34\"/>\n+ <reg name=\"f3\" bitsize=\"32\" type=\"ieee_single\" regnum=\"35\"/>\n+ <reg name=\"f4\" bitsize=\"32\" type=\"ieee_single\" regnum=\"36\"/>\n+ <reg name=\"f5\" bitsize=\"32\" type=\"ieee_single\" regnum=\"37\"/>\n+ <reg name=\"f6\" bitsize=\"32\" type=\"ieee_single\" regnum=\"38\"/>\n+ <reg name=\"f7\" bitsize=\"32\" type=\"ieee_single\" regnum=\"39\"/>\n+ <reg name=\"f8\" bitsize=\"32\" type=\"ieee_single\" regnum=\"40\"/>\n+ <reg name=\"f9\" bitsize=\"32\" type=\"ieee_single\" regnum=\"41\"/>\n+ <reg name=\"f10\" bitsize=\"32\" type=\"ieee_single\" regnum=\"42\"/>\n+ <reg name=\"f11\" bitsize=\"32\" type=\"ieee_single\" regnum=\"43\"/>\n+ <reg name=\"f12\" bitsize=\"32\" type=\"ieee_single\" regnum=\"44\"/>\n+ <reg name=\"f13\" bitsize=\"32\" type=\"ieee_single\" regnum=\"45\"/>\n+ <reg name=\"f14\" bitsize=\"32\" type=\"ieee_single\" regnum=\"46\"/>\n+ <reg name=\"f15\" bitsize=\"32\" type=\"ieee_single\" regnum=\"47\"/>\n+ <reg name=\"f16\" bitsize=\"32\" type=\"ieee_single\" regnum=\"48\"/>\n+ <reg name=\"f17\" bitsize=\"32\" type=\"ieee_single\" regnum=\"49\"/>\n+ <reg name=\"f18\" bitsize=\"32\" type=\"ieee_single\" regnum=\"50\"/>\n+ <reg name=\"f19\" bitsize=\"32\" type=\"ieee_single\" regnum=\"51\"/>\n+ <reg name=\"f20\" bitsize=\"32\" type=\"ieee_single\" regnum=\"52\"/>\n+ <reg name=\"f21\" bitsize=\"32\" type=\"ieee_single\" regnum=\"53\"/>\n+ <reg name=\"f22\" bitsize=\"32\" type=\"ieee_single\" regnum=\"54\"/>\n+ <reg name=\"f23\" bitsize=\"32\" type=\"ieee_single\" regnum=\"55\"/>\n+ <reg name=\"f24\" bitsize=\"32\" type=\"ieee_single\" regnum=\"56\"/>\n+ <reg name=\"f25\" bitsize=\"32\" type=\"ieee_single\" regnum=\"57\"/>\n+ <reg name=\"f26\" bitsize=\"32\" type=\"ieee_single\" regnum=\"58\"/>\n+ <reg name=\"f27\" bitsize=\"32\" type=\"ieee_single\" regnum=\"59\"/>\n+ <reg name=\"f28\" bitsize=\"32\" type=\"ieee_single\" regnum=\"60\"/>\n+ <reg name=\"f29\" bitsize=\"32\" type=\"ieee_single\" regnum=\"61\"/>\n+ <reg name=\"f30\" bitsize=\"32\" type=\"ieee_single\" regnum=\"62\"/>\n+ <reg name=\"f31\" bitsize=\"32\" type=\"ieee_single\" regnum=\"63\"/>\n+\n+ <reg name=\"f32\" bitsize=\"64\" type=\"ieee_double\" regnum=\"64\"/>\n+ <reg name=\"f34\" bitsize=\"64\" type=\"ieee_double\" regnum=\"65\"/>\n+ <reg name=\"f36\" bitsize=\"64\" type=\"ieee_double\" regnum=\"66\"/>\n+ <reg name=\"f38\" bitsize=\"64\" type=\"ieee_double\" regnum=\"67\"/>\n+ <reg name=\"f40\" bitsize=\"64\" type=\"ieee_double\" regnum=\"68\"/>\n+ <reg name=\"f42\" bitsize=\"64\" type=\"ieee_double\" regnum=\"69\"/>\n+ <reg name=\"f44\" bitsize=\"64\" type=\"ieee_double\" regnum=\"70\"/>\n+ <reg name=\"f46\" bitsize=\"64\" type=\"ieee_double\" regnum=\"71\"/>\n+ <reg name=\"f48\" bitsize=\"64\" type=\"ieee_double\" regnum=\"72\"/>\n+ <reg name=\"f50\" bitsize=\"64\" type=\"ieee_double\" regnum=\"73\"/>\n+ <reg name=\"f52\" bitsize=\"64\" type=\"ieee_double\" regnum=\"74\"/>\n+ <reg name=\"f54\" bitsize=\"64\" type=\"ieee_double\" regnum=\"75\"/>\n+ <reg name=\"f56\" bitsize=\"64\" type=\"ieee_double\" regnum=\"76\"/>\n+ <reg name=\"f58\" bitsize=\"64\" type=\"ieee_double\" regnum=\"77\"/>\n+ <reg name=\"f60\" bitsize=\"64\" type=\"ieee_double\" regnum=\"78\"/>\n+ <reg name=\"f62\" bitsize=\"64\" type=\"ieee_double\" regnum=\"79\"/>\n+</feature>\n", "prefixes": [ "03/11" ] }