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GET /api/patches/2197071/?format=api
{ "id": 2197071, "url": "http://patchwork.ozlabs.org/api/patches/2197071/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216225228.53959-7-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216225228.53959-7-philmd@linaro.org>", "list_archive_url": null, "date": "2026-02-16T22:52:22", "name": "[06/11] target/sparc: Expose gdbstub registers to sparc32 targets", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2eb1978b7d6610b8711dd23159329ac3f6506757", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216225228.53959-7-philmd@linaro.org/mbox/", "series": [ { "id": 492361, "url": "http://patchwork.ozlabs.org/api/series/492361/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492361", "date": "2026-02-16T22:52:16", "name": "monitor/hmp: Automatically handle gdb-xml exposed registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492361/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197071/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197071/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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I9HXf1atU2yMjtvMLVNIPjMcSRP+rR5ymoYPRPbqOS6Q5W5cYMLJRmbZmP2+cIYvc95Vdu8cE88\n ZRMtJdwP/+GW3nQFpaHSXxOiHTrznzRXcQ1DBtit/rhtblkAwhmNwgr3y2S+a4fEm2kkq4vaEd", "X-Received": "by 2002:a05:600c:8b2f:b0:47d:885d:d2ff with SMTP id\n 5b1f17b1804b1-48379c1faccmr122104925e9.29.1771282396044;\n Mon, 16 Feb 2026 14:53:16 -0800 (PST)", "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "Laurent Vivier <laurent@vivier.eu>,\n \"Dr. David Alan Gilbert\" <dave@treblig.org>,\n Nicholas Piggin <npiggin@gmail.com>, Chinmay Rath <rathc@linux.ibm.com>,\n\t=?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>,\n Zhao Liu <zhao1.liu@intel.com>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Artyom Tarasenko <atar4qemu@gmail.com>,\n Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>,\n Gustavo Romero <gustavo.romero@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>, unisono@quyllur.org, =?utf-8?q?Philipp?=\n\t=?utf-8?q?e_Mathieu-Daud=C3=A9?= <philmd@linaro.org>, qemu-ppc@nongnu.org", "Subject": "[PATCH 06/11] target/sparc: Expose gdbstub registers to sparc32\n targets", "Date": "Mon, 16 Feb 2026 23:52:22 +0100", "Message-ID": "<20260216225228.53959-7-philmd@linaro.org>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20260216225228.53959-1-philmd@linaro.org>", "References": "<20260216225228.53959-1-philmd@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::343;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x343.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Import gdb-xml/sparc32-{cpu,fpu,cp0}.xml from mainstream binutils,\ntag 'binutils-2_46', found in the gdb/features/sparc/folder [*].\n\nRegister them by setting the CPUClass::gdb_core_xml_file field and\ncalling gdb_register_coprocessor() in sparc_cpu_register_gdb_regs().\n\n[*] https://sourceware.org/git/?p=binutils-gdb.git;a=tree;f=gdb/features/sparc;hb=refs/tags/binutils-2_46\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n configs/targets/sparc-linux-user.mak | 1 +\n configs/targets/sparc-softmmu.mak | 1 +\n target/sparc/cpu.c | 3 +-\n target/sparc/gdbstub.c | 13 +++++----\n gdb-xml/sparc32-cp0.xml | 18 ++++++++++++\n gdb-xml/sparc32-cpu.xml | 42 ++++++++++++++++++++++++++++\n gdb-xml/sparc32-fpu.xml | 42 ++++++++++++++++++++++++++++\n 7 files changed, 114 insertions(+), 6 deletions(-)\n create mode 100644 gdb-xml/sparc32-cp0.xml\n create mode 100644 gdb-xml/sparc32-cpu.xml\n create mode 100644 gdb-xml/sparc32-fpu.xml", "diff": "diff --git a/configs/targets/sparc-linux-user.mak b/configs/targets/sparc-linux-user.mak\nindex d3f0716ca2d..01446e28783 100644\n--- a/configs/targets/sparc-linux-user.mak\n+++ b/configs/targets/sparc-linux-user.mak\n@@ -2,5 +2,6 @@ TARGET_ARCH=sparc\n TARGET_SYSTBL_ABI=common,32\n TARGET_SYSTBL=syscall.tbl\n TARGET_BIG_ENDIAN=y\n+TARGET_XML_FILES=gdb-xml/sparc32-cpu.xml gdb-xml/sparc32-fpu.xml gdb-xml/sparc32-cp0.xml\n TARGET_LONG_BITS=32\n TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y\ndiff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak\nindex c4c38946d54..ed846735f41 100644\n--- a/configs/targets/sparc-softmmu.mak\n+++ b/configs/targets/sparc-softmmu.mak\n@@ -1,5 +1,6 @@\n TARGET_ARCH=sparc\n TARGET_BIG_ENDIAN=y\n+TARGET_XML_FILES=gdb-xml/sparc32-cpu.xml gdb-xml/sparc32-fpu.xml gdb-xml/sparc32-cp0.xml\n TARGET_LONG_BITS=32\n TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y\n TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y\ndiff --git a/target/sparc/cpu.c b/target/sparc/cpu.c\nindex 08ebbd3640b..ec454affaad 100644\n--- a/target/sparc/cpu.c\n+++ b/target/sparc/cpu.c\n@@ -1096,7 +1096,8 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)\n cc->gdb_core_xml_file = \"sparc64-cpu.xml\";\n cc->gdb_num_core_regs = 32;\n #else\n- cc->gdb_num_core_regs = 72;\n+ cc->gdb_core_xml_file = \"sparc32-cpu.xml\";\n+ cc->gdb_num_core_regs = 32;\n #endif\n cc->tcg_ops = &sparc_tcg_ops;\n }\ndiff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c\nindex b5b1494950a..ed52e521dcc 100644\n--- a/target/sparc/gdbstub.c\n+++ b/target/sparc/gdbstub.c\n@@ -43,7 +43,6 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n return 0;\n }\n \n-__attribute__((unused))\n static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n {\n CPUSPARCState *env = cpu_env(cs);\n@@ -79,7 +78,6 @@ static int sparc_fpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n return 0;\n }\n \n-__attribute__((unused))\n static int sparc_cp0_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n {\n CPUSPARCState *env = cpu_env(cs);\n@@ -154,7 +152,6 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n #endif\n }\n \n-__attribute__((unused))\n static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n {\n CPUSPARCState *env = cpu_env(cs);\n@@ -197,7 +194,6 @@ static int sparc_fpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n #endif\n }\n \n-__attribute__((unused))\n static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n {\n CPUSPARCState *env = cpu_env(cs);\n@@ -271,7 +267,14 @@ static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n void sparc_cpu_register_gdb_regs(CPUState *cs)\n {\n #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n- /* Not yet supported */\n+ gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,\n+ sparc_fpu_gdb_write_register,\n+ gdb_find_static_feature(\"sparc32-fpu.xml\"),\n+ 0);\n+ gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,\n+ sparc_cp0_gdb_write_register,\n+ gdb_find_static_feature(\"sparc32-cp0.xml\"),\n+ 0);\n #else\n gdb_register_coprocessor(cs, sparc_fpu_gdb_read_register,\n sparc_fpu_gdb_write_register,\ndiff --git a/gdb-xml/sparc32-cp0.xml b/gdb-xml/sparc32-cp0.xml\nnew file mode 100644\nindex 00000000000..eacd89cf3b5\n--- /dev/null\n+++ b/gdb-xml/sparc32-cp0.xml\n@@ -0,0 +1,18 @@\n+<?xml version=\"1.0\"?>\n+<!-- Copyright (C) 2013-2026 Free Software Foundation, Inc.\n+\n+ Copying and distribution of this file, with or without modification,\n+ are permitted in any medium without royalty provided the copyright\n+ notice and this notice are preserved. -->\n+\n+<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">\n+<feature name=\"org.gnu.gdb.sparc.cp0\">\n+ <reg name=\"y\" bitsize=\"32\" type=\"uint32\" regnum=\"64\"/>\n+ <reg name=\"psr\" bitsize=\"32\" type=\"uint32\" regnum=\"65\"/>\n+ <reg name=\"wim\" bitsize=\"32\" type=\"uint32\" regnum=\"66\"/>\n+ <reg name=\"tbr\" bitsize=\"32\" type=\"uint32\" regnum=\"67\"/>\n+ <reg name=\"pc\" bitsize=\"32\" type=\"code_ptr\" regnum=\"68\"/>\n+ <reg name=\"npc\" bitsize=\"32\" type=\"code_ptr\" regnum=\"69\"/>\n+ <reg name=\"fsr\" bitsize=\"32\" type=\"uint32\" regnum=\"70\"/>\n+ <reg name=\"csr\" bitsize=\"32\" type=\"uint32\" regnum=\"71\"/>\n+</feature>\ndiff --git a/gdb-xml/sparc32-cpu.xml b/gdb-xml/sparc32-cpu.xml\nnew file mode 100644\nindex 00000000000..242295c886e\n--- /dev/null\n+++ b/gdb-xml/sparc32-cpu.xml\n@@ -0,0 +1,42 @@\n+<?xml version=\"1.0\"?>\n+<!-- Copyright (C) 2013-2026 Free Software Foundation, Inc.\n+\n+ Copying and distribution of this file, with or without modification,\n+ are permitted in any medium without royalty provided the copyright\n+ notice and this notice are preserved. -->\n+\n+<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">\n+<feature name=\"org.gnu.gdb.sparc.cpu\">\n+ <reg name=\"g0\" bitsize=\"32\" type=\"uint32\" regnum=\"0\"/>\n+ <reg name=\"g1\" bitsize=\"32\" type=\"uint32\" regnum=\"1\"/>\n+ <reg name=\"g2\" bitsize=\"32\" type=\"uint32\" regnum=\"2\"/>\n+ <reg name=\"g3\" bitsize=\"32\" type=\"uint32\" regnum=\"3\"/>\n+ <reg name=\"g4\" bitsize=\"32\" type=\"uint32\" regnum=\"4\"/>\n+ <reg name=\"g5\" bitsize=\"32\" type=\"uint32\" regnum=\"5\"/>\n+ <reg name=\"g6\" bitsize=\"32\" type=\"uint32\" regnum=\"6\"/>\n+ <reg name=\"g7\" bitsize=\"32\" type=\"uint32\" regnum=\"7\"/>\n+ <reg name=\"o0\" bitsize=\"32\" type=\"uint32\" regnum=\"8\"/>\n+ <reg name=\"o1\" bitsize=\"32\" type=\"uint32\" regnum=\"9\"/>\n+ <reg name=\"o2\" bitsize=\"32\" type=\"uint32\" regnum=\"10\"/>\n+ <reg name=\"o3\" bitsize=\"32\" type=\"uint32\" regnum=\"11\"/>\n+ <reg name=\"o4\" bitsize=\"32\" type=\"uint32\" regnum=\"12\"/>\n+ <reg name=\"o5\" bitsize=\"32\" type=\"uint32\" regnum=\"13\"/>\n+ <reg name=\"sp\" bitsize=\"32\" type=\"uint32\" regnum=\"14\"/>\n+ <reg name=\"o7\" bitsize=\"32\" type=\"uint32\" regnum=\"15\"/>\n+ <reg name=\"l0\" bitsize=\"32\" type=\"uint32\" regnum=\"16\"/>\n+ <reg name=\"l1\" bitsize=\"32\" type=\"uint32\" regnum=\"17\"/>\n+ <reg name=\"l2\" bitsize=\"32\" type=\"uint32\" regnum=\"18\"/>\n+ <reg name=\"l3\" bitsize=\"32\" type=\"uint32\" regnum=\"19\"/>\n+ <reg name=\"l4\" bitsize=\"32\" type=\"uint32\" regnum=\"20\"/>\n+ <reg name=\"l5\" bitsize=\"32\" type=\"uint32\" regnum=\"21\"/>\n+ <reg name=\"l6\" bitsize=\"32\" type=\"uint32\" regnum=\"22\"/>\n+ <reg name=\"l7\" bitsize=\"32\" type=\"uint32\" regnum=\"23\"/>\n+ <reg name=\"i0\" bitsize=\"32\" type=\"uint32\" regnum=\"24\"/>\n+ <reg name=\"i1\" bitsize=\"32\" type=\"uint32\" regnum=\"25\"/>\n+ <reg name=\"i2\" bitsize=\"32\" type=\"uint32\" regnum=\"26\"/>\n+ <reg name=\"i3\" bitsize=\"32\" type=\"uint32\" regnum=\"27\"/>\n+ <reg name=\"i4\" bitsize=\"32\" type=\"uint32\" regnum=\"28\"/>\n+ <reg name=\"i5\" bitsize=\"32\" type=\"uint32\" regnum=\"29\"/>\n+ <reg name=\"fp\" bitsize=\"32\" type=\"uint32\" regnum=\"30\"/>\n+ <reg name=\"i7\" bitsize=\"32\" type=\"uint32\" regnum=\"31\"/>\n+</feature>\ndiff --git a/gdb-xml/sparc32-fpu.xml b/gdb-xml/sparc32-fpu.xml\nnew file mode 100644\nindex 00000000000..38217ca7a92\n--- /dev/null\n+++ b/gdb-xml/sparc32-fpu.xml\n@@ -0,0 +1,42 @@\n+<?xml version=\"1.0\"?>\n+<!-- Copyright (C) 2013-2026 Free Software Foundation, Inc.\n+\n+ Copying and distribution of this file, with or without modification,\n+ are permitted in any medium without royalty provided the copyright\n+ notice and this notice are preserved. -->\n+\n+<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">\n+<feature name=\"org.gnu.gdb.sparc.fpu\">\n+ <reg name=\"f0\" bitsize=\"32\" type=\"ieee_single\" regnum=\"32\"/>\n+ <reg name=\"f1\" bitsize=\"32\" type=\"ieee_single\" regnum=\"33\"/>\n+ <reg name=\"f2\" bitsize=\"32\" type=\"ieee_single\" regnum=\"34\"/>\n+ <reg name=\"f3\" bitsize=\"32\" type=\"ieee_single\" regnum=\"35\"/>\n+ <reg name=\"f4\" bitsize=\"32\" type=\"ieee_single\" regnum=\"36\"/>\n+ <reg name=\"f5\" bitsize=\"32\" type=\"ieee_single\" regnum=\"37\"/>\n+ <reg name=\"f6\" bitsize=\"32\" type=\"ieee_single\" regnum=\"38\"/>\n+ <reg name=\"f7\" bitsize=\"32\" type=\"ieee_single\" regnum=\"39\"/>\n+ <reg name=\"f8\" bitsize=\"32\" type=\"ieee_single\" regnum=\"40\"/>\n+ <reg name=\"f9\" bitsize=\"32\" type=\"ieee_single\" regnum=\"41\"/>\n+ <reg name=\"f10\" bitsize=\"32\" type=\"ieee_single\" regnum=\"42\"/>\n+ <reg name=\"f11\" bitsize=\"32\" type=\"ieee_single\" regnum=\"43\"/>\n+ <reg name=\"f12\" bitsize=\"32\" type=\"ieee_single\" regnum=\"44\"/>\n+ <reg name=\"f13\" bitsize=\"32\" type=\"ieee_single\" regnum=\"45\"/>\n+ <reg name=\"f14\" bitsize=\"32\" type=\"ieee_single\" regnum=\"46\"/>\n+ <reg name=\"f15\" bitsize=\"32\" type=\"ieee_single\" regnum=\"47\"/>\n+ <reg name=\"f16\" bitsize=\"32\" type=\"ieee_single\" regnum=\"48\"/>\n+ <reg name=\"f17\" bitsize=\"32\" type=\"ieee_single\" regnum=\"49\"/>\n+ <reg name=\"f18\" bitsize=\"32\" type=\"ieee_single\" regnum=\"50\"/>\n+ <reg name=\"f19\" bitsize=\"32\" type=\"ieee_single\" regnum=\"51\"/>\n+ <reg name=\"f20\" bitsize=\"32\" type=\"ieee_single\" regnum=\"52\"/>\n+ <reg name=\"f21\" bitsize=\"32\" type=\"ieee_single\" regnum=\"53\"/>\n+ <reg name=\"f22\" bitsize=\"32\" type=\"ieee_single\" regnum=\"54\"/>\n+ <reg name=\"f23\" bitsize=\"32\" type=\"ieee_single\" regnum=\"55\"/>\n+ <reg name=\"f24\" bitsize=\"32\" type=\"ieee_single\" regnum=\"56\"/>\n+ <reg name=\"f25\" bitsize=\"32\" type=\"ieee_single\" regnum=\"57\"/>\n+ <reg name=\"f26\" bitsize=\"32\" type=\"ieee_single\" regnum=\"58\"/>\n+ <reg name=\"f27\" bitsize=\"32\" type=\"ieee_single\" regnum=\"59\"/>\n+ <reg name=\"f28\" bitsize=\"32\" type=\"ieee_single\" regnum=\"60\"/>\n+ <reg name=\"f29\" bitsize=\"32\" type=\"ieee_single\" regnum=\"61\"/>\n+ <reg name=\"f30\" bitsize=\"32\" type=\"ieee_single\" regnum=\"62\"/>\n+ <reg name=\"f31\" bitsize=\"32\" type=\"ieee_single\" regnum=\"63\"/>\n+</feature>\n", "prefixes": [ "06/11" ] }