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GET /api/patches/2197066/?format=api
{ "id": 2197066, "url": "http://patchwork.ozlabs.org/api/patches/2197066/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260216225228.53959-2-philmd@linaro.org/", "project": { "id": 69, "url": "http://patchwork.ozlabs.org/api/projects/69/?format=api", "name": "QEMU powerpc development", "link_name": "qemu-ppc", "list_id": "qemu-ppc.nongnu.org", "list_email": "qemu-ppc@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216225228.53959-2-philmd@linaro.org>", "list_archive_url": null, "date": "2026-02-16T22:52:17", "name": "[01/11] target/sparc: Introduce sparc_cpu_register_gdb_regs() stub", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "74a902389ceb70621a8ec8d45d971b0df645573f", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260216225228.53959-2-philmd@linaro.org/mbox/", "series": [ { "id": 492360, "url": "http://patchwork.ozlabs.org/api/series/492360/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-ppc/list/?series=492360", "date": "2026-02-16T22:52:16", "name": "monitor/hmp: Automatically handle gdb-xml exposed registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492360/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2197066/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197066/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=JpQ35XCz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::336;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-ppc@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-ppc.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-ppc>", "List-Post": "<mailto:qemu-ppc@nongnu.org>", "List-Help": "<mailto:qemu-ppc-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Introduce sparc_cpu_register_gdb_regs() which we are going\nto fill in the next commits.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/sparc/cpu.h | 1 +\n target/sparc/cpu.c | 2 ++\n target/sparc/gdbstub.c | 9 +++++++++\n 3 files changed, 12 insertions(+)", "diff": "diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h\nindex 7169a502432..0139732e4cc 100644\n--- a/target/sparc/cpu.h\n+++ b/target/sparc/cpu.h\n@@ -586,6 +586,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);\n void sparc_cpu_do_interrupt(CPUState *cpu);\n int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\n int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n+void sparc_cpu_register_gdb_regs(CPUState *cs);\n G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,\n MMUAccessType access_type,\n int mmu_idx,\ndiff --git a/target/sparc/cpu.c b/target/sparc/cpu.c\nindex 3991681d1d1..f58d0298966 100644\n--- a/target/sparc/cpu.c\n+++ b/target/sparc/cpu.c\n@@ -897,6 +897,8 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)\n return;\n }\n \n+ sparc_cpu_register_gdb_regs(cs);\n+\n qemu_init_vcpu(cs);\n \n scc->parent_realize(dev, errp);\ndiff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c\nindex 134617fb232..79d661fbc10 100644\n--- a/target/sparc/gdbstub.c\n+++ b/target/sparc/gdbstub.c\n@@ -215,3 +215,12 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n return 8;\n #endif\n }\n+\n+void sparc_cpu_register_gdb_regs(CPUState *cs)\n+{\n+#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n+ /* Not yet supported */\n+#else\n+ /* Not yet supported */\n+#endif\n+}\n", "prefixes": [ "01/11" ] }