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GET /api/patches/2197060/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2197060,
    "url": "http://patchwork.ozlabs.org/api/patches/2197060/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216225228.53959-3-philmd@linaro.org/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260216225228.53959-3-philmd@linaro.org>",
    "list_archive_url": null,
    "date": "2026-02-16T22:52:18",
    "name": "[02/11] target/sparc: Restore 'gdb-xml/sparc64-cp0.xml'",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "3050e372d2bf629d5807ff94cc775670b418ada7",
    "submitter": {
        "id": 85046,
        "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api",
        "name": "Philippe Mathieu-Daudé",
        "email": "philmd@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216225228.53959-3-philmd@linaro.org/mbox/",
    "series": [
        {
            "id": 492361,
            "url": "http://patchwork.ozlabs.org/api/series/492361/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492361",
            "date": "2026-02-16T22:52:16",
            "name": "monitor/hmp: Automatically handle gdb-xml exposed registers",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/492361/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2197060/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2197060/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "Laurent Vivier <laurent@vivier.eu>,\n \"Dr. David Alan Gilbert\" <dave@treblig.org>,\n Nicholas Piggin <npiggin@gmail.com>, Chinmay Rath <rathc@linux.ibm.com>,\n\t=?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>,\n Zhao Liu <zhao1.liu@intel.com>,\n Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Artyom Tarasenko <atar4qemu@gmail.com>,\n Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>,\n Gustavo Romero <gustavo.romero@linaro.org>,\n Paolo Bonzini <pbonzini@redhat.com>, unisono@quyllur.org, =?utf-8?q?Philipp?=\n\t=?utf-8?q?e_Mathieu-Daud=C3=A9?= <philmd@linaro.org>, qemu-ppc@nongnu.org",
        "Subject": "[PATCH 02/11] target/sparc: Restore 'gdb-xml/sparc64-cp0.xml'",
        "Date": "Mon, 16 Feb 2026 23:52:18 +0100",
        "Message-ID": "<20260216225228.53959-3-philmd@linaro.org>",
        "X-Mailer": "git-send-email 2.52.0",
        "In-Reply-To": "<20260216225228.53959-1-philmd@linaro.org>",
        "References": "<20260216225228.53959-1-philmd@linaro.org>",
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    },
    "content": "Restore gdb-xml/sparc64-cp0.xml from mainstream binutils, tag\n'binutils-2_46', found in the gdb/features/sparc/folder [*].\n\nExtract sparc_cp0_gdb_write_register() out of\nsparc_cpu_gdb_read_register() and sparc_cp0_gdb_write_register()\nout of sparc_cpu_gdb_write_register(), taking care to update the\nregister indexes in the switch cases.\n\nRegister these helpers with a call to gdb_register_coprocessor()\nin sparc_cpu_register_gdb_regs().\n\n[*] https://sourceware.org/git/?p=binutils-gdb.git;a=tree;f=gdb/features/sparc;hb=refs/tags/binutils-2_46\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n configs/targets/sparc64-linux-user.mak |   2 +-\n configs/targets/sparc64-softmmu.mak    |   2 +-\n target/sparc/cpu.c                     |   2 +-\n target/sparc/gdbstub.c                 | 193 ++++++++++++++-----------\n gdb-xml/sparc64-core.xml               |   7 -\n gdb-xml/sparc64-cp0.xml                |  16 ++\n 6 files changed, 131 insertions(+), 91 deletions(-)\n create mode 100644 gdb-xml/sparc64-cp0.xml",
    "diff": "diff --git a/configs/targets/sparc64-linux-user.mak b/configs/targets/sparc64-linux-user.mak\nindex 3bbd8495210..930f7e13ab9 100644\n--- a/configs/targets/sparc64-linux-user.mak\n+++ b/configs/targets/sparc64-linux-user.mak\n@@ -4,6 +4,6 @@ TARGET_ABI_DIR=sparc\n TARGET_SYSTBL_ABI=common,64\n TARGET_SYSTBL=syscall.tbl\n TARGET_BIG_ENDIAN=y\n-TARGET_XML_FILES=gdb-xml/sparc64-core.xml\n+TARGET_XML_FILES=gdb-xml/sparc64-core.xml gdb-xml/sparc64-cp0.xml\n TARGET_LONG_BITS=64\n TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y\ndiff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak\nindex 8a0290c2093..22e7f3c94a7 100644\n--- a/configs/targets/sparc64-softmmu.mak\n+++ b/configs/targets/sparc64-softmmu.mak\n@@ -1,7 +1,7 @@\n TARGET_ARCH=sparc64\n TARGET_BASE_ARCH=sparc\n TARGET_BIG_ENDIAN=y\n-TARGET_XML_FILES=gdb-xml/sparc64-core.xml\n+TARGET_XML_FILES=gdb-xml/sparc64-core.xml gdb-xml/sparc64-cp0.xml\n TARGET_LONG_BITS=64\n TARGET_NOT_USING_LEGACY_LDST_PHYS_API=y\n TARGET_NOT_USING_LEGACY_NATIVE_ENDIAN_API=y\ndiff --git a/target/sparc/cpu.c b/target/sparc/cpu.c\nindex f58d0298966..6f7b250abb3 100644\n--- a/target/sparc/cpu.c\n+++ b/target/sparc/cpu.c\n@@ -1094,7 +1094,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)\n \n #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)\n     cc->gdb_core_xml_file = \"sparc64-core.xml\";\n-    cc->gdb_num_core_regs = 86;\n+    cc->gdb_num_core_regs = 80;\n #else\n     cc->gdb_num_core_regs = 72;\n #endif\ndiff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c\nindex 79d661fbc10..bdd759dd0a9 100644\n--- a/target/sparc/gdbstub.c\n+++ b/target/sparc/gdbstub.c\n@@ -18,6 +18,7 @@\n  * License along with this library; if not, see <http://www.gnu.org/licenses/>.\n  */\n #include \"qemu/osdep.h\"\n+#include \"exec/gdbstub.h\"\n #include \"cpu.h\"\n #include \"gdbstub/helpers.h\"\n \n@@ -48,27 +49,6 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n             return gdb_get_reg32(mem_buf, env->fpr[(n - 32) / 2].l.upper);\n         }\n     }\n-    /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */\n-    switch (n) {\n-    case 64:\n-        return gdb_get_rega(mem_buf, env->y);\n-    case 65:\n-        return gdb_get_rega(mem_buf, cpu_get_psr(env));\n-    case 66:\n-        return gdb_get_rega(mem_buf, env->wim);\n-    case 67:\n-        return gdb_get_rega(mem_buf, env->tbr);\n-    case 68:\n-        return gdb_get_rega(mem_buf, env->pc);\n-    case 69:\n-        return gdb_get_rega(mem_buf, env->npc);\n-    case 70:\n-        return gdb_get_rega(mem_buf, cpu_get_fsr(env));\n-    case 71:\n-        return gdb_get_rega(mem_buf, 0); /* csr */\n-    default:\n-        return gdb_get_rega(mem_buf, 0);\n-    }\n #else\n     if (n < 64) {\n         /* f0-f31 */\n@@ -87,21 +67,51 @@ int sparc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n          */\n         return gdb_get_reg64(mem_buf, env->fpr[(n - 64) + 16].ll);\n     }\n+#endif\n+    return 0;\n+}\n+\n+__attribute__((unused))\n+static int sparc_cp0_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n+{\n+    CPUSPARCState *env = cpu_env(cs);\n+\n+#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n+    /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */\n     switch (n) {\n-    case 80:\n+    case 0:\n+        return gdb_get_rega(mem_buf, env->y);\n+    case 1:\n+        return gdb_get_rega(mem_buf, cpu_get_psr(env));\n+    case 2:\n+        return gdb_get_rega(mem_buf, env->wim);\n+    case 3:\n+        return gdb_get_rega(mem_buf, env->tbr);\n+    case 4:\n+        return gdb_get_rega(mem_buf, env->pc);\n+    case 5:\n+        return gdb_get_rega(mem_buf, env->npc);\n+    case 6:\n+        return gdb_get_rega(mem_buf, cpu_get_fsr(env));\n+    case 7:\n+        return gdb_get_rega(mem_buf, 0); /* csr */\n+    }\n+#else\n+    switch (n) {\n+    case 0:\n         return gdb_get_regl(mem_buf, env->pc);\n-    case 81:\n+    case 1:\n         return gdb_get_regl(mem_buf, env->npc);\n-    case 82:\n+    case 2:\n         return gdb_get_regl(mem_buf, (cpu_get_ccr(env) << 32) |\n                                      ((env->asi & 0xff) << 24) |\n                                      ((env->pstate & 0xfff) << 8) |\n                                      cpu_get_cwp64(env));\n-    case 83:\n+    case 3:\n         return gdb_get_regl(mem_buf, cpu_get_fsr(env));\n-    case 84:\n+    case 4:\n         return gdb_get_regl(mem_buf, env->fprs);\n-    case 85:\n+    case 5:\n         return gdb_get_regl(mem_buf, env->y);\n     }\n #endif\n@@ -138,33 +148,6 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n         } else {\n             env->fpr[(n - 32) / 2].l.upper = tmp;\n         }\n-    } else {\n-        /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */\n-        switch (n) {\n-        case 64:\n-            env->y = tmp;\n-            break;\n-        case 65:\n-            cpu_put_psr(env, tmp);\n-            break;\n-        case 66:\n-            env->wim = tmp;\n-            break;\n-        case 67:\n-            env->tbr = tmp;\n-            break;\n-        case 68:\n-            env->pc = tmp;\n-            break;\n-        case 69:\n-            env->npc = tmp;\n-            break;\n-        case 70:\n-            cpu_put_fsr(env, tmp);\n-            break;\n-        default:\n-            return 0;\n-        }\n     }\n     return 4;\n #else\n@@ -185,32 +168,77 @@ int sparc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n          * n == 79: f62 : env->fpr[31]\n          */\n         env->fpr[(n - 64) + 16].ll = tmp;\n-    } else {\n-        switch (n) {\n-        case 80:\n-            env->pc = tmp;\n-            break;\n-        case 81:\n-            env->npc = tmp;\n-            break;\n-        case 82:\n-            cpu_put_ccr(env, tmp >> 32);\n-            env->asi = (tmp >> 24) & 0xff;\n-            env->pstate = (tmp >> 8) & 0xfff;\n-            cpu_put_cwp64(env, tmp & 0xff);\n-            break;\n-        case 83:\n-            cpu_put_fsr(env, tmp);\n-            break;\n-        case 84:\n-            env->fprs = tmp;\n-            break;\n-        case 85:\n-            env->y = tmp;\n-            break;\n-        default:\n-            return 0;\n-        }\n+    }\n+    return 8;\n+#endif\n+}\n+\n+__attribute__((unused))\n+static int sparc_cp0_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n+{\n+    CPUSPARCState *env = cpu_env(cs);\n+\n+#if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n+    uint32_t tmp;\n+\n+    tmp = ldl_p(mem_buf);\n+\n+    /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */\n+    switch (n) {\n+    case 0:\n+        env->y = tmp;\n+        break;\n+    case 1:\n+        cpu_put_psr(env, tmp);\n+        break;\n+    case 2:\n+        env->wim = tmp;\n+        break;\n+    case 3:\n+        env->tbr = tmp;\n+        break;\n+    case 4:\n+        env->pc = tmp;\n+        break;\n+    case 5:\n+        env->npc = tmp;\n+        break;\n+    case 6:\n+        cpu_put_fsr(env, tmp);\n+        break;\n+    default:\n+        return 0;\n+    }\n+    return 4;\n+#else\n+    uint64_t tmp;\n+\n+    tmp = ldq_p(mem_buf);\n+\n+    switch (n) {\n+    case 0:\n+        env->pc = tmp;\n+        break;\n+    case 1:\n+        env->npc = tmp;\n+        break;\n+    case 2:\n+        cpu_put_ccr(env, tmp >> 32);\n+        env->asi = (tmp >> 24) & 0xff;\n+        env->pstate = (tmp >> 8) & 0xfff;\n+        cpu_put_cwp64(env, tmp & 0xff);\n+        break;\n+    case 3:\n+        cpu_put_fsr(env, tmp);\n+        break;\n+    case 4:\n+        env->fprs = tmp;\n+        break;\n+    case 5:\n+        env->y = tmp;\n+        break;\n+    default:\n+        return 0;\n     }\n     return 8;\n #endif\n@@ -221,6 +249,9 @@ void sparc_cpu_register_gdb_regs(CPUState *cs)\n #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)\n     /* Not yet supported */\n #else\n-    /* Not yet supported */\n+    gdb_register_coprocessor(cs, sparc_cp0_gdb_read_register,\n+                             sparc_cp0_gdb_write_register,\n+                             gdb_find_static_feature(\"sparc64-cp0.xml\"),\n+                             0);\n #endif\n }\ndiff --git a/gdb-xml/sparc64-core.xml b/gdb-xml/sparc64-core.xml\nindex 375b9bb0cc6..1c26d8c01c1 100644\n--- a/gdb-xml/sparc64-core.xml\n+++ b/gdb-xml/sparc64-core.xml\n@@ -89,11 +89,4 @@\n   <reg name=\"f58\" bitsize=\"64\" type=\"ieee_double\" regnum=\"77\"/>\n   <reg name=\"f60\" bitsize=\"64\" type=\"ieee_double\" regnum=\"78\"/>\n   <reg name=\"f62\" bitsize=\"64\" type=\"ieee_double\" regnum=\"79\"/>\n-\n-  <reg name=\"pc\" bitsize=\"64\" type=\"code_ptr\" regnum=\"80\"/>\n-  <reg name=\"npc\" bitsize=\"64\" type=\"code_ptr\" regnum=\"81\"/>\n-  <reg name=\"state\" bitsize=\"64\" type=\"uint64\" regnum=\"82\"/>\n-  <reg name=\"fsr\" bitsize=\"64\" type=\"uint64\" regnum=\"83\"/>\n-  <reg name=\"fprs\" bitsize=\"64\" type=\"uint64\" regnum=\"84\"/>\n-  <reg name=\"y\" bitsize=\"64\" type=\"uint64\" regnum=\"85\"/>\n </feature>\ndiff --git a/gdb-xml/sparc64-cp0.xml b/gdb-xml/sparc64-cp0.xml\nnew file mode 100644\nindex 00000000000..9b938dc7ecc\n--- /dev/null\n+++ b/gdb-xml/sparc64-cp0.xml\n@@ -0,0 +1,16 @@\n+<?xml version=\"1.0\"?>\n+<!-- Copyright (C) 2013-2026 Free Software Foundation, Inc.\n+\n+     Copying and distribution of this file, with or without modification,\n+     are permitted in any medium without royalty provided the copyright\n+     notice and this notice are preserved.  -->\n+\n+<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">\n+<feature name=\"org.gnu.gdb.sparc.cp0\">\n+  <reg name=\"pc\" bitsize=\"64\" type=\"code_ptr\" regnum=\"80\"/>\n+  <reg name=\"npc\" bitsize=\"64\" type=\"code_ptr\" regnum=\"81\"/>\n+  <reg name=\"state\" bitsize=\"64\" type=\"uint64\" regnum=\"82\"/>\n+  <reg name=\"fsr\" bitsize=\"64\" type=\"uint64\" regnum=\"83\"/>\n+  <reg name=\"fprs\" bitsize=\"64\" type=\"uint64\" regnum=\"84\"/>\n+  <reg name=\"y\" bitsize=\"64\" type=\"uint64\" regnum=\"85\"/>\n+</feature>\n",
    "prefixes": [
        "02/11"
    ]
}