Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2196940/?format=api
{ "id": 2196940, "url": "http://patchwork.ozlabs.org/api/patches/2196940/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216-phys_addr-v5-6-29d522f1339c@rev.ng/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260216-phys_addr-v5-6-29d522f1339c@rev.ng>", "list_archive_url": null, "date": "2026-02-16T16:28:43", "name": "[v5,6/7] hw/riscv: Set IOMMU PAS via property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0a035440bf3dbd1dcca72af154aeed2382b4f419", "submitter": { "id": 92408, "url": "http://patchwork.ozlabs.org/api/people/92408/?format=api", "name": "Anton Johansson", "email": "anjo@rev.ng" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260216-phys_addr-v5-6-29d522f1339c@rev.ng/mbox/", "series": [ { "id": 492329, "url": "http://patchwork.ozlabs.org/api/series/492329/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=492329", "date": "2026-02-16T16:28:43", "name": "[v5,1/7] target/hppa: Define PA[20|1X] physical address space size", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/492329/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2196940/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2196940/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n unprotected) header.d=rev.ng header.i=@rev.ng header.a=rsa-sha256\n header.s=dkim header.b=n+37FUAW;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fF7S62qQ3z1xwF\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 17 Feb 2026 03:25:57 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vs1Pq-00006g-OH; Mon, 16 Feb 2026 11:25:43 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <anjo@rev.ng>) id 1vs1Pf-00005i-TQ\n for qemu-devel@nongnu.org; Mon, 16 Feb 2026 11:25:32 -0500", "from rev.ng ([94.130.142.21])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <anjo@rev.ng>) id 1vs1Pd-0002xX-W1\n for qemu-devel@nongnu.org; Mon, 16 Feb 2026 11:25:31 -0500" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng;\n s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding:\n Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID:\n Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc\n :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe:\n List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post:\n List-Help; bh=EVTOqHa20xkuN8pbowvDJdQiy3xQO6bUDITFnBaSXuc=; b=n+37FUAWwKePGs0\n nHPsT1rEsDG5UTRFExjNetqQ1HVDvqmevsCz0Ixavwm7LUmHUbL+aboAOKSm6jQX6REprCS3VQy3Q\n 1wGlY6toz6bVtjP4I4AUCA5Trinb0VTrPEWH94O9YwB1kP7LTSQ4D8lR+Qt15mOPzvNGws2AeCaAL\n Qo=;", "Date": "Mon, 16 Feb 2026 17:28:43 +0100", "Subject": "[PATCH v5 6/7] hw/riscv: Set IOMMU PAS via property", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260216-phys_addr-v5-6-29d522f1339c@rev.ng>", "References": "<20260216-phys_addr-v5-0-29d522f1339c@rev.ng>", "In-Reply-To": "<20260216-phys_addr-v5-0-29d522f1339c@rev.ng>", "To": "qemu-devel@nongnu.org", "Cc": "=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n Richard Henderson <richard.henderson@linaro.org>,\n Helge Deller <deller@gmx.de>, Paolo Bonzini <pbonzini@redhat.com>,\n Song Gao <gaosong@loongson.cn>, Bibo Mao <maobibo@loongson.cn>,\n Palmer Dabbelt <palmer@dabbelt.com>,\n Alistair Francis <alistair.francis@wdc.com>,\n Brian Cain <brian.cain@oss.qualcomm.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, Anton Johansson <anjo@rev.ng>", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1771259335; l=4218;\n i=anjo@rev.ng; s=20260210; h=from:subject:message-id;\n bh=RhMMm25hymELLHUlU6FHekc0cJ209Hl5oXPKQXPtiO8=;\n b=d2IrUkT1+OR9FQ3dSt4Cc6vW4nBFIpYOVw+i8TUxpXisJ9xQvLSytdC6rxvryAk/KGm13W+hk\n LpcLaUSj7mPDJnV+2JeW9U6oEjwxWXmN6WIowLmthSuf/I3GipGaDBD", "X-Developer-Key": "i=anjo@rev.ng; a=ed25519;\n pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow=", "Received-SPF": "pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng;\n helo=rev.ng", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Reply-to": "Anton Johansson <anjo@rev.ng>", "From": "Anton Johansson via qemu development <qemu-devel@nongnu.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Replaces the only remaining use of TARGET_PHYS_ADDR_SPACE_BITS for RISCV\nwith a property RISCVIOMMUState::pas_bits that gets written to the\ncapabilities field upon device realization. This write needs to happen\nat realize-time to ensure the property has been set.\n\nFor the virt machine and sysbus device, pas_bits is set by\nvirt_machine_init() to either 34 or 56 bits, retaining previous behaviour.\nHowever, for the PCI device we do not have access to the CPU state, and\ninstead use the maximum riscv64 value of 56 bits.\n\nSigned-off-by: Anton Johansson <anjo@rev.ng>\n---\n hw/riscv/riscv-iommu.h | 1 +\n hw/riscv/riscv-iommu-pci.c | 3 +++\n hw/riscv/riscv-iommu.c | 8 ++++----\n hw/riscv/virt.c | 7 +++++++\n 4 files changed, 15 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h\nindex 2dabd86941..2a9f6fccd5 100644\n--- a/hw/riscv/riscv-iommu.h\n+++ b/hw/riscv/riscv-iommu.h\n@@ -34,6 +34,7 @@ struct RISCVIOMMUState {\n /*< public >*/\n uint32_t version; /* Reported interface version number */\n uint32_t pid_bits; /* process identifier width */\n+ uint32_t pas_bits; /* physical address bits */\n uint32_t bus; /* PCI bus mapping for non-root endpoints */\n \n uint64_t cap; /* IOMMU supported capabilities */\ndiff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c\nindex 5f7d359204..14dd5f3857 100644\n--- a/hw/riscv/riscv-iommu-pci.c\n+++ b/hw/riscv/riscv-iommu-pci.c\n@@ -158,6 +158,9 @@ static void riscv_iommu_pci_init(Object *obj)\n \n iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS;\n riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI);\n+\n+ /* Report maximum physical address size of riscv64 */\n+ iommu->pas_bits = 56;\n }\n \n static const Property riscv_iommu_pci_properties[] = {\ndiff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c\nindex b46b337375..98345b1280 100644\n--- a/hw/riscv/riscv-iommu.c\n+++ b/hw/riscv/riscv-iommu.c\n@@ -2453,10 +2453,6 @@ static void riscv_iommu_instance_init(Object *obj)\n /* Enable translation debug interface */\n s->cap = RISCV_IOMMU_CAP_DBG;\n \n- /* Report QEMU target physical address space limits */\n- s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS,\n- TARGET_PHYS_ADDR_SPACE_BITS);\n-\n /* TODO: method to report supported PID bits */\n s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */\n s->cap |= RISCV_IOMMU_CAP_PD8;\n@@ -2487,6 +2483,9 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp)\n {\n RISCVIOMMUState *s = RISCV_IOMMU(dev);\n \n+ /* Report QEMU target physical address space limits. */\n+ s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, s->pas_bits);\n+\n s->cap |= s->version & RISCV_IOMMU_CAP_VERSION;\n if (s->enable_msi) {\n s->cap |= RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF;\n@@ -2645,6 +2644,7 @@ void riscv_iommu_reset(RISCVIOMMUState *s)\n static const Property riscv_iommu_properties[] = {\n DEFINE_PROP_UINT32(\"version\", RISCVIOMMUState, version,\n RISCV_IOMMU_SPEC_DOT_VER),\n+ DEFINE_PROP_UINT32(\"pas-bits\", RISCVIOMMUState, pas_bits, 0),\n DEFINE_PROP_UINT32(\"bus\", RISCVIOMMUState, bus, 0x0),\n DEFINE_PROP_UINT32(\"ioatc-limit\", RISCVIOMMUState, iot_limit,\n LIMIT_CACHE_IOT),\ndiff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex 07e66b3936..bbce2fb667 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -1739,6 +1739,13 @@ static void virt_machine_init(MachineState *machine)\n object_property_set_link(OBJECT(iommu_sys), \"irqchip\",\n OBJECT(mmio_irqchip),\n &error_fatal);\n+ /*\n+ * For riscv64 use a physical address size of 56 bits (44 bit PPN),\n+ * and for riscv32 use 34 bits (22 bit PPN).\n+ */\n+ object_property_set_uint(OBJECT(iommu_sys), \"pas-bits\",\n+ riscv_is_32bit(&s->soc[0]) ? 34 : 56,\n+ &error_fatal);\n \n sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal);\n }\n", "prefixes": [ "v5", "6/7" ] }